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Computer Arithmetic - Volume Iii [Kõva köide]

Edited by (The Univ Of Texas At Austin, Usa), Edited by (Qualcomm, Austin, Usa)
  • Formaat: Hardback, 472 pages
  • Ilmumisaeg: 27-Apr-2015
  • Kirjastus: World Scientific Publishing Co Pte Ltd
  • ISBN-10: 9814651133
  • ISBN-13: 9789814651134
Teised raamatud teemal:
Computer Arithmetic - Volume IiiSuurem pilt
  • Formaat: Hardback, 472 pages
  • Ilmumisaeg: 27-Apr-2015
  • Kirjastus: World Scientific Publishing Co Pte Ltd
  • ISBN-10: 9814651133
  • ISBN-13: 9789814651134
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9789814651134.html
Märksõnad:
Computer Arithmetic Volume III is a compilation of key papers in computer arithmetic on floating-point arithmetic and design. The intent is to show progress, evolution, and novelty in the area of floating-point arithmetic. This field has made extraordinary progress since the initial software routines on mainframe computers have evolved into hardware implementations in processors spanning a wide range of performance. Nevertheless, these papers pave the way to the understanding of modern day processors design where computer arithmetic are supported by floating-point units. The goal of Volume III is to collect the defining document for floating-point arithmetic and many of the key papers on the implementation of both binary and decimal floating-point arithmetic into a single volume. Although fewer than forty papers are included, their reference lists will direct the interested reader to other excellent work that could not be included here.Volume III is specifically oriented to the needs of designers and users of both general-purpose computers and special-purpose digital processors. The book should also be useful to systems engineers, computer architects, and logic designers. It is also intended to serve as a primary text for a course on floating-point arithmetic, as well as a supplementary text for courses in digital arithmetic and high-speed signal processing.
About the Editors v
Preface vii
Contents by Author ix
Introduction xvii
Part I OVERVIEW
Editors' Comments on Paper 1
1(2)
1 IEEE Standard for Floating-Point Arithmetic, ANSI/IEEE Std.754--2008, The Institute of Electrical and Electronic Engineers, Inc., New York, Aug., 2008
3(70)
Part II FLOATING-POINT ADDITION
Editors' Comments on Papers 2 Through 7
73(2)
2 "Delay-Optimized Implementation of IEEE Floating-Point Addition," IEEE Transactions on Computers, vol. 53, pp. 97--113, 2004
75(18)
P. M. Seidel
G. Even
3 "Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition," Proceedings of the 15th IEEE Symposium on Computer Arithmetic, pp. 203--210, 2001
93(8)
J. D. Bruguera
T. Lang
4 "Reduced Latency IEEE Floating-Point Standard Adder Architectures," Proceedings of the 14th IEEE Symposium on Computer Arithmetic, pp. 35--43, 1999
101(8)
A. Beaumont-Smith
N. Burgess
S. Lefrere
C. Lim
5 "Leading-Zero Anticipatory Logic for High-Speed Floating-Point Addition," Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pp. 589--592
109(8)
H. Suzuki
H. Makino
K. Mashiko
H. Hamano
6 "Leading Zero Anticipation and Detection -- A Comparison of Methods," Proceedings of the 15th IEEE Symposium on Computer Arithmetic, pp. 7--12, 2001
117(6)
M. Schmookler
K. Nowka
7 "S/370 Sign-Magnitude Floating-Point Adder," IEEE Journal of Solid-State Circuits, vol. 24, pp. 1062--1070, 1989
123(10)
S. Vassiliadis
D. S. Lemon
M. Putrino
Part III FLOATING-POINT MULTIPLICATION
Editors' Comments on Papers 8 Through 10
133(2)
8 "A Quadruple Precision and Dual Double Precision Floating-Point Multiplier," Euromicro Symposium on Digital System Design, pp. 76--81, 2003
135(6)
A. Akkas
M. J. Schulte
9 "A Dual Mode IEEE Multiplier," IEEE 2nd Int. Conference on Innovative Systems in Silicon, pp. 282--289. 1997
141(8)
G. Even
S. M. Mueller
P. M. Seidel
10 "167 MHz Radix-4 Floating-Point Multiplier," Proceedings of the 12th Symposium on Computer Arithmetic, pp. 149--154, 1995
149(6)
R. K. Yu
G. B. Zyner
Part IV ROUNDING
Editors' Comments on Papers 11 Through 14
155(2)
11 "Rounding Algorithms for IEEE Multipliers," Proceedings of the 9th Symposium on Computer Arithmetic, pp. 176--183, 1989
157(8)
M. R. Santoro
G. Bewick
M. A. Horowitz
12 "Systematic IEEE Rounding Method for High-Speed Floating-Point Multipliers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, pp. 511--521, 2004
165(12)
N. T. Quach
N. Takagi
M. J. Flynn
13 "A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication," IEEE Transactions on Computers, vol. 49, pp. 638--650, 2000
177(14)
G. Even
P. M. Seidel
14 "Prenormalization Rounding in IEEE Floating-Point Operations Using a Flagged Prefix Adder," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, pp. 266--277, 2005
191(12)
N. Burgess
Part V FUSED MULTIPLY ADD
Editors' Comments on Papers 15 Through 19
203(2)
15 "Design of the IBM RISC System/6000 Floating-Point Execution Unit," IBM Journal of Research and Development, vol. 34, pp. 59--70, 1990
205(12)
R. K. Montoye
E. Hokenek
S. L. Runyon
16 "A 17 × 69 Bit Multiply and Add Unit with Redundant Binary Feedback and Single Cycle Latency," Proceedings 11th Symposium on Computer Arithmetic, pp. 163--170, 1993
217(8)
W. S. Briggs
D. Matula
17 "Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units," IEEE Transactions on Computers, vol. 47, pp. 927--937, 1998
225(12)
R. Jessani
M. Putrino
18 "Floating-Point Fused Multiply-Add with Reduced Latency," IEEE Transactions on Computers, vol. 53, pp. 988--1003, 2004
237(6)
T. Lang
J. D. Bruguera
19 "Floating-Point Fused Multiply-Add Architectures," Forty-First Asilomar Conference on Signals, Systems and Computers, pp. 331--337, 2007
243(8)
E. Quinnell
E. E. Swartzlander, Jr.
C. Lemonds
Part VI FLOATING-POINT DIVISION
Editors' Comments on Papers 20 Through 25
251(2)
20 "Floating-Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor," Proceedings of the 14th IEEE Symposium on Computer Arithmetic, pp. 106--115, 1999
253(10)
S. F. Oberman
21 "High Performance Floating-Point Unit with 116 bit Wide Divider," Proceedings of the 16th IEEE Symposium on Computer Arithmetic, pp. 87--94, 2003
263(8)
G. Gerwig
H. Wetter
E. M. Schwarz
J. Haess
22 "High-Speed Double-Precision Computation of Reciprocal, Division, Square Root, and Inverse Square Root," IEEE Transactions on Computers, vol. 51, pp. 1377--1388, 2002
271(12)
J. A. Pineiro
J. D. Bruguera
23 "167 MHz Radix-8 Floating-Point Divide and Square Root Using Overlapped Radix-2 Stages," Proceedings 12th Symposium on Computer Arithmetic, pp. 155--162, 1995
283(8)
J. Prabhu
G. Zyner
24 "Division Algorithms and Implementations," IEEE Transactions on Computers, vol. 46, pp. 833--854, 1997
291(22)
S. F. Oberman
M. J. Flynn
25 "Faithful Interpolation in Reciprocal Tables," Proceedings 13th Symposium on Computer Arithmetic, pp. 82--91, 1997
313(10)
D. Das Sarma
D. W. Matula
Part VII ELEMENTARY FUNCTIONS
Editors' Comments on Papers 26 Through 32
323(2)
26 "Computation of Elementary Functions on the IBM RISC System/6000 Processor," IBM Journal of Research and Development, vol. 34, pp. 111--119, 1990
325(10)
P. W. Markstein
27 "Accurate and Monotone Approximations of Some Transcendental Functions," Proceedings of the 10th Symposium on Computer Arithmetic, pp. 237--244, 1991
335(8)
W. Ferguson
T. Brightman
28 "The K5 Transcendental Functions," Proceedings of the 12th Symposium on Computer Arithmetic, pp. 163--170, 1995
343(8)
T. Lynch
A. Ahmed
M. Schulte
T. Callaway
R. Tisdale
29 "Hardware Designs for Exactly Rounded Elementary Functions," IEEE Transactions on Computers, vol. 43, pp. 964--973, 1994
351(10)
M. J. Schulte
E. E. Swartzlander, Jr.
30 "Toward Correctly Rounded Transcendentals," IEEE Transactions on Computers, vol. 47, pp. 1235--1243, 1998
361(10)
V. Lefevre
J.-M. Muller
A. Tisserand
31 "Reciprocation, Square Root, Inverse Square Root and Some Elementary Functions Using Small Multipliers," IEEE Transactions on Computers, vol. 49, pp. 628--637, 2000
371(10)
M. Ercegovac
T. Lang
J.-M. Muller
A. Tisserand
32 "Multipartite Table Methods," IEEE Transactions on Computers, vol. 54, pp. 319--330, 2005
381(12)
F. Dinechin
A. Tisserand
Part VIII DECIMAL FLOATING-POINT ARITHMETIC
Editors' Comments on Papers 33 Through 37
393(2)
33 "A Decimal Floating-Point Specification," Proceedings of the 15th IEEE Symposium on Computer Arithmetic, pp. 147--154, 2001
395(8)
M. F. Cowlishaw
E. M. Schwarz
R. M. Smith
C. F. Webb
34 "Decimal Floating-Point: Algorism for Computers," Proceedings of the 16th IEEE Symposium on Computer Arithmetic, pp. 104--111, 2003
403(8)
M. F. Cowlishaw
35 "A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoded Format," Proceedings of the 18th IEEE Symposium on Computer Arithmetic, pp. 29--37, 2007
411(10)
M. Cornea
C. Anderson
J. Harrison
P.-T. P. Tang
E. Schneider
C. Tsen
36 "Decimal Floating-Point Multiplication," IEEE Transactions on Computers, vol. 58, pp. 902--916, 2009
421(16)
M. A. Erie
B. J. Hickmann
M. J. Schulte
37 "A Survey of Hardware Designs for Decimal Arithmetic," IBM Journal of Research and Development, vol. 54, pp. 8:1--8:14, 2010
437
L.-K. Wang
M. A. Erie
C. Tsen
E. M. Schwarz
M. J. Schulte