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Computer Organization, Design, and Architecture, Fifth Edition 5th edition [Kõva köide]

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  • Formaat: Hardback, 725 pages, kõrgus x laius: 254x178 mm, kaal: 1516 g, 103 Tables, black and white; 575 Illustrations, black and white
  • Ilmumisaeg: 20-Dec-2013
  • Kirjastus: CRC Press Inc
  • ISBN-10: 1466585544
  • ISBN-13: 9781466585546
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Computer Organization, Design, and Architecture, Fifth Edition 5th editionSuurem pilt
  • Formaat: Hardback, 725 pages, kõrgus x laius: 254x178 mm, kaal: 1516 g, 103 Tables, black and white; 575 Illustrations, black and white
  • Ilmumisaeg: 20-Dec-2013
  • Kirjastus: CRC Press Inc
  • ISBN-10: 1466585544
  • ISBN-13: 9781466585546
Teised raamatud teemal:
Teised raamatud sellest sooduspakkumisest: Taylor & Francis teadusraamatud International Student Editions hindadega
Püsilink: https://www.kriso.ee/db/9781466585546.html
Suitable for a one- or two-semester undergraduate or beginning graduate course in computer science and computer engineering, Computer Organization, Design, and Architecture, Fifth Edition presents the operating principles, capabilities, and limitations of digital computers to enable the development of complex yet efficient systems. With 11 new sections and four revised sections, this edition takes students through a solid, up-to-date exploration of single- and multiple-processor systems, embedded architectures, and performance evaluation.

See Whats New in the Fifth Edition











Expanded coverage of embedded systems, mobile processors, and cloud computing

Material for the "Architecture and Organization" part of the 2013 IEEE/ACM Draft Curricula for Computer Science and Engineering Updated commercial machine architecture examples

The backbone of the book is a description of the complete design of a simple but complete hypothetical computer. The author then details the architectural features of contemporary computer systems (selected from Intel, MIPS, ARM, Motorola, Cray and various microcontrollers, etc.) as enhancements to the structure of the simple computer. He also introduces performance enhancements and advanced architectures including networks, distributed systems, GRIDs, and cloud computing.

Computer organization deals with providing just enough details on the operation of the computer system for sophisticated users and programmers. Often, books on digital systems architecture fall into four categories: logic design, computer organization, hardware design, and system architecture. This book captures the important attributes of these four categories to present a comprehensive text that includes pertinent hardware, software, and system aspects.

Arvustused

Praise for the Previous Edition

"I am convinced that the book will serve well as a handbook for courses on the fundamentals of computer architecture and organization." Antoni Michalski, Zentralblatt Math, 2008

Preface xix
Chapter 1 Introduction
1(12)
1.1 Computer System Organization
1(3)
1.1.1 Hardware
2(1)
1.1.2 Software
2(1)
1.1.3 System
3(1)
1.2 Computer Evolution
4(5)
1.2.1 von Neumann Model
5(2)
1.2.2 Generations of Computer Technology
7(1)
1.2.3 Moore's Law
8(1)
1.3 Organization versus Design versus Architecture
9(1)
1.4 Performance Evaluation
9(2)
1.4.1 Benchmarks
10(1)
1.5 Summary
11(2)
Problems
11(1)
Bibliography
12(1)
Chapter 2 Number Systems and Codes
13(9)
2.1 Number Systems
13(4)
2.1.1 Binary System
14(2)
2.1.2 Octal System
16(1)
2.1.3 Hexadecimal System
17(1)
2.2 Conversion
17(5)
2.2.1 Radix Divide Technique
17(1)
2.2.2 Radix Multiply Technique
18(2)
2.2.3 Base 2k Conversion
20(2)
2.3 Arithmetic
22(1)
2.3.1 Binary Arithmetic
22(1)
2.3.1.1 Addition
22(1)
2.3.1.2 Subtraction
23(1)
2.3.1.3 Multiplication
23(1)
2.3.1.4 Division
24(1)
2.3.1.5 Shifting
25(15)
2.3.2 Octal Arithmetic
25(2)
2.3.3 Hexadecimal Arithmetic
27(3)
2.4 Sign--Magnitude System
30(1)
2.5 Complement Number System
30(7)
2.5.1 2s Complement Addition
34(1)
2.5.2 1s Complement Addition
35(1)
2.5.3 Shifting Revisited
35(2)
2.5.4 Comparison of Complement Systems
37(1)
2.6 Floating-Point Numbers
37(3)
2.6.1 IEEE Standard
39(1)
2.6.1.1 Single Precision
40(2)
2.6.1.2 Double Precision
42(1)
2.6.1.3 Comparison
42(1)
2.6.1.4 Rounding
42(1)
2.6.1.5 Accuracy
43(1)
2.6.1.6 Exceptions
44(15)
2.7 Binary Codes
45(4)
2.7.1 Weighted Codes
45(2)
2.7.2 Nonweighted Codes
47(1)
2.7.3 Error-Detection Codes
48(1)
2.7.4 Alphanumeric Codes
49(1)
2.8 Data Storage and Register Transfer
49(3)
2.9 Representation of Numbers, Arrays, and Records
52(3)
2.9.1 BCD Numbers
53(1)
2.9.2 Floating-Point Numbers
53(1)
2.9.3 Representation of Strings
53(1)
2.9.4 Arrays
54(1)
2.9.5 Records
54(1)
2.10 Summary
55(4)
Problems
55(2)
Bibliography
57(2)
Chapter 3 Combinational Logic
59(58)
3.1 Basic Operations and Terminology
59(7)
3.1.1 Evaluation of Expressions
61(1)
3.1.2 Truth Tables
62(1)
3.1.3 Functions and Their Representation
62(2)
3.1.4 Canonical Forms
64(2)
3.2 Boolean Algebra (Switching Algebra)
66(1)
3.3 Minimization of Boolean Functions
67(14)
3.3.1 Venn Diagrams
67(1)
3.3.2 Karnaugh Maps
68(11)
3.3.3 Quine--McCluskey Procedure
79(2)
3.4 Primitive Hardware Blocks
81(1)
3.5 Functional Analysis of Combinational Circuits
82(3)
3.6 Synthesis of Combinational Circuits
85(5)
3.6.1 AND--OR Circuits
86(1)
3.6.2 OR--AND Circuits
86(2)
3.6.3 NAND--NAND and NOR--NOR Circuits
88(2)
3.7 Some Popular Combinational Circuits
90(8)
3.7.1 Adders
90(3)
3.7.2 Decoders
93(1)
3.7.3 Code Converters
94(1)
3.7.4 Encoders
94(1)
3.7.5 Multiplexers
95(1)
3.7.6 Demultiplexers
96(2)
3.8 Integrated Circuits
98(12)
3.8.1 Positive and Negative Logic
99(2)
3.8.2 Signal Inversion
101(1)
3.8.3 Other Characteristics
101(4)
3.8.4 Special Outputs
105(3)
3.8.5 Designing with ICs
108(2)
3.9 Loading and Timing
110(2)
3.10 Summary
112(5)
Problems
113(3)
Bibliography
116(1)
Chapter 4 Synchronous Sequential Circuits
117(54)
4.1 Flip-Flops
119(6)
4.1.1 Set--Reset Flip-Flop
119(3)
4.1.2 D Flip-Flop
122(1)
4.1.3 JK Flip-Flop
123(1)
4.1.4 T Flip-Flop
123(1)
4.1.5 Characteristic and Excitation Tables
123(2)
4.2 Timing Characteristics of Flip-Flops
125(5)
4.2.1 Master--Slave Flip-Flops
127(1)
4.2.2 Edge-Triggered Flip-Flops
128(2)
4.3 Flip-Flop ICs
130(1)
4.4 Analysis of Synchronous Sequential Circuits
130(8)
4.5 Design of Synchronous Sequential Circuits
138(4)
4.6 Registers
142(8)
4.7 Register Transfer Logic
150(2)
4.8 Register Transfer Schemes
152(3)
4.8.1 Point-to-Point Transfer
152(2)
4.8.2 Bus Transfer
154(1)
4.9 Register Transfer Languages
155(5)
4.10 Designing Sequential Circuits with Integrated Circuits
160(1)
4.11 Programmable Logic
160(11)
4.11.1 Circuit Implementation Modes and Devices
165(1)
4.11.2 Programmable Logic Arrays
166(2)
4.11.3 Programmable Array Logic
168(3)
4.11.3.1 Altera Complex PLDs (CPLDs)
171(5)
4.11.4 Gate Arrays
174(2)
4.11.4.1 Xilinx SRAM-Based FPGAs
176(7)
4.12 Summary
179(4)
Problems
179(3)
Bibliography
182(1)
Chapter 5 A Simple Computer: Organization and Programming
183(32)
5.1 A Simple Computer
183(13)
5.1.1 Data Format
186(1)
5.1.2 Instruction Format
187(1)
5.1.3 Instruction Set
187(4)
5.1.4 Addressing Modes
191(4)
5.1.5 Other Addressing Modes
195(1)
5.1.6 Addressing Limitations
195(1)
5.1.7 Machine Language Programming
195(1)
5.2 ASC Assembler
196(6)
5.2.1 Assembly Process
199(3)
5.3 Program Loading
202(2)
5.4 Subroutines
204(3)
5.5 Macros
207(1)
5.6 Linkers and Loaders
208(3)
5.6.1 Dynamic Linking
209(2)
5.7 Summary
211(4)
Problems
211(3)
Bibliography
214(1)
Chapter 6 A Simple Computer: Hardware Design
215(44)
6.1 Program Execution
215(1)
6.1.1 Instruction Fetch
216(1)
6.1.2 Instruction Execution
216(1)
6.2 Data, Instruction, and Address Flow
216(4)
6.2.1 Fetch Phase
216(3)
6.2.2 Address Calculations
219(1)
6.2.3 Execution Phase
220(1)
6.3 Bus Structure
220(3)
6.4 Arithmetic and Logic Unit
223(4)
6.5 Input/Output
227(1)
6.6 Control Unit
227(13)
6.6.1 Types of Control Units
229(1)
6.6.2 Hardwired Control Unit for ASC
230(1)
6.6.3 Memory versus Processor Speed
230(1)
6.6.4 Machine Cycles
230(5)
6.6.5 One-Address Instructions
235(1)
6.6.6 Zero-Address Instructions
235(1)
6.6.7 Input/Output Instructions
235(5)
6.7 Console
240(7)
6.8 Microprogrammed Control Unit (MCU)
247(9)
6.8.1 Microprogrammed Control Unit for ASC
247(9)
6.9 Summary
256(3)
Problems
256(2)
Bibliography
258(1)
Chapter 7 Input/Output
259(20)
7.1 General I/O Model
259(4)
7.2 I/O Function
263(5)
7.2.1 Timing
263(2)
7.2.2 Control
265(2)
7.2.3 Data Conversion
267(1)
7.2.4 Error Detection and Correction
267(1)
7.3 Interrupts
268(7)
7.3.1 Interrupt Mechanism for ASC
269(2)
7.3.2 Multiple Interrupts
271(1)
7.3.3 Polling
271(1)
7.3.4 Vectored Interrupts
271(3)
7.3.5 Types of Interrupt Structures
274(1)
7.4 Direct-Memory Access
275(3)
7.5 Bus Architecture
278(1)
7.5.1 Bus Control (Arbitration)
278(1)
7.5.2 Bus Standards
278(1)
7.5.2.1 Multibus I
279(2)
7.5.2.2 Multibus II
281(3)
7.5.2.3 VMEbus
284(14)
7.6 Channels
287(1)
7.7 I/O Processors
288(3)
7.7.1 IOP Organization
290(1)
7.8 Serial I/O
291(2)
7.9 Common I/O Devices
293(5)
7.9.1 Terminals
294(1)
7.9.2 Mouse
294(1)
7.9.3 Printers
294(1)
7.9.4 Scanners
295(1)
7.9.5 A/D and D/A Converters
296(1)
7.9.6 Tapes and Disks
296(1)
7.9.7 Touchpads and Trackpads
297(1)
7.9.8 Touch Screens
297(1)
7.9.9 Gaming Console
297(1)
7.10 Examples
298(1)
7.10.1 Motorola 68000 (MC68000)
298(1)
7.10.1.1 Programmed I/O on MC68000
298(3)
7.10.1.2 MC68000 interrupt system
301(2)
7.10.1.3 MC68000 DMA
303(12)
7.10.2 Intel 21285
303(7)
7.10.3 Control Data 6600
310(2)
7.11 Summary
312(3)
Problems
312(2)
Bibliography
314(1)
Chapter 8 Processor and Instruction-Set Architectures
315(29)
8.1 Types of Computer Systems
315(1)
8.2 Operand (Data) Types and Formats
316(3)
8.2.1 Fixed Point
316(1)
8.2.2 Decimal Data
316(1)
8.2.3 Character Strings
317(1)
8.2.4 Floating-Point Numbers
317(1)
8.2.5 Endian
318(1)
8.2.6 Register versus Memory Storage
318(1)
8.3 Registers
319(3)
8.4 Instruction Set
322(8)
8.4.1 Instruction Types
322(1)
8.4.2 Instruction Length
323(2)
8.4.3 Opcode Selection
325(2)
8.4.4 Instruction Formats
327(3)
8.5 Addressing Modes
330(3)
8.5.1 Immediate Addressing
330(1)
8.5.2 Paged Addressing
330(1)
8.5.3 Base-Register Addressing
331(1)
8.5.4 Relative Addressing
331(1)
8.5.5 Implied (Implicit) Addressing
331(2)
8.6 Instruction-Set Orthogonality
333(1)
8.7 RISC versus CISC
333(3)
8.8 Example Systems
336(8)
8.8.1 Intel 8080
336(5)
8.8.2 Intel 8086
341(1)
8.8.3 Intel Pentium
342(2)
8.8.3.1 Instruction Set
344(2)
8.8.3.2 Hardware Architecture
346(5)
8.8.3.3 MMX Technology
351(6)
8.9 Summary
353(4)
Problems
353(2)
Bibliography
355(2)
Chapter 9 Memory and Storage
357(10)
9.1 Types of Memory
357(6)
9.1.1 RAM
358(1)
9.1.2 Content-Addressable Memory
359(1)
9.1.3 Sequential-Access Memory
360(3)
9.1.4 Direct-Access Memory
363(1)
9.2 Memory System Parameters
363(2)
9.3 Memory Hierarchy
365(1)
9.4 Memory Devices and Organizations
366(1)
9.4.1 RAM Devices
367(1)
9.4.1.1 Static RAM
367(1)
9.4.1.2 Dynamic Memory
368(4)
9.4.1.3 Read-Only Memory
372(4)
9.4.2 Associative Memory
373(1)
9.4.3 Sequential-Access Memory Devices
374(2)
9.4.4 Direct-Access Storage Devices
376(1)
9.4.4.1 Magnetic Disk
376(1)
9.4.4.2 SSDs
376(3)
9.4.4.3 Redundant Array of Independent Disks
379(4)
9.4.4.4 Optical Disks
383(7)
9.5 Memory System Design Using ICs
384(1)
9.6 Speed Enhancement
385(5)
9.6.1 Banking
386(1)
9.6.2 Interleaving
387(1)
9.6.3 Multiport Memories
387(1)
9.6.4 Wider-Word Fetch
388(1)
9.6.5 Instruction Buffer
388(1)
9.6.6 Cache Memory
389(1)
9.6.6.1 Address Translation
390(1)
9.6.6.2 Address Mapping Function
391(2)
9.6.6.3 Replacement Algorithm
393(2)
9.6.6.4 Write Operations
395(1)
9.6.6.5 Performance
395(17)
9.7 Size Enhancement
396(5)
9.7.1 Page Size
397(1)
9.7.2 Speed
398(1)
9.7.3 Address Translation
398(3)
9.8 Address Extension
401(1)
9.9 Example Systems
402(10)
9.9.1 Memory Management in Intel Processors
402(9)
9.9.2 Intel Sandy Bridge Cache Hierarchy
411(1)
9.9.2.1 Loads
412(1)
9.9.2.2 Stores
413(1)
9.9.2.3 LID Cache
413(1)
9.9.2.4 Loads
414(1)
9.9.2.5 Stores
415(1)
9.9.2.6 Address Translation
415(1)
9.9.2.7 Store Forwarding
415(1)
9.9.2.8 Memory Disambiguation
416(1)
9.9.2.9 Bank Conflict
416(9)
9.9.3 Motorola 68020 Memory Management
416(1)
9.9.4 Sun-3 System Memory Management
417(3)
9.10 Summary
420(5)
Problems
421(2)
Bibliography
423(2)
Chapter 10 Arithmetic/Logic Unit Enhancement
425(24)
10.1 Logical and Fixed-Point Binary Operations
425(8)
10.1.1 Logic Operations
425(1)
10.1.2 Addition and Subtraction
426(1)
10.1.3 Multiplication
427(3)
10.1.4 Division
430(1)
10.1.5 Stack-Based ALU
431(2)
10.2 Decimal Arithmetic
433(2)
10.3 Pipelining
435(1)
10.4 ALU with Multiple Functional Units
436(1)
10.5 Example Systems
437(12)
10.5.1 Multifunction ALU IC (74181)
438(1)
10.5.2 Texas Instruments' MSP430 Hardware Multiplier
439(5)
10.5.3 Motorola 68881 Coprocessor
444(2)
10.5.4 Control Data 6600
446(2)
10.5.5 Architecture of the Cray Series
448(1)
10.5.5.1 Memory
449(1)
10.5.5.2 Processor Interconnection
449(1)
10.5.5.3 Central Processor
449(7)
10.5.5.4 Instruction Fetch
456(1)
10.5.5.5 I/O System
456(1)
10.5.5.6 Other Systems in the Series
456(3)
10.6 Summary
457(2)
Problems
457(1)
Bibliography
458(1)
Chapter 11 Control Unit Enhancement
459(14)
11.1 Speed Enhancement
459(3)
11.1.1 Instruction Cycle Speedup
460(1)
11.1.2 Instruction Execution Overlap
460(2)
11.1.3 Parallel Instruction Execution
462(1)
11.1.4 Instruction Buffer and Cache
462(1)
11.2 Hardwired versus Microprogrammed Control Units
462(2)
11.3 Pipeline Performance Issues
464(9)
11.3.1 Data Interlocks
468(5)
11.3.2 Conditional Branches
473(1)
11.3.2.1 Branch Prediction
473(1)
11.3.2.2 Delayed Branching
473(1)
11.3.2.3 Branch-Prediction Buffer
474(1)
11.3.2.4 Branch History
475(1)
11.3.2.5 Multiple Instruction Buffers
475(2)
11.3.3 Interrupts
476(1)
11.3.4 Instruction Deferral
477(1)
11.3.4.1 CDC 6600 Scoreboard
477(4)
11.4 Example Systems
478(3)
11.4.1 Motorola MC88100/88200
478(3)
11.4.2 MIPS R10000 Architecture
481(1)
11.4.2.1 Instruction Set (MIPS IV)
481(1)
11.4.2.2 Superscalar Pipeline
482(3)
11.4.2.3 Functional Units
485(1)
11.4.2.4 Pipeline Stages
485(2)
11.4.2.5 Cache
487(2)
11.4.2.6 Processor-Operating Modes
489(4)
11.4.2.7 Floating-Point Units
493(2)
11.4.2.8 Interrupts
495(3)
11.4.3 Intel Corporation's Itanium
496(2)
11.4.3.1 Registers
498(2)
11.4.3.2 Memory
500(1)
11.4.3.3 Instruction Package
501(1)
11.4.3.4 Instruction Set Transition Model
501(3)
11.4.4 Other Intel Processors
503(1)
11.4.4.1 Intel NetBurst Microarchitecture
504(2)
11.4.4.2 Intel Core Microarchitecture
506(2)
11.4.4.3 Intel Atom Microarchitecture
508(1)
11.4.4.4 Intel Microarchitecture Code Name Nehalem
508(1)
11.4.5 Intel Microarchitecture Code Name Sandy Bridge
509(1)
11.4.5.1 Intel Microarchitecture Code Name Sandy Bridge Pipeline Overview
509(2)
11.4.5.2 Front End
511(4)
11.4.5.3 Out-of-Order Engine
515(1)
11.4.5.4 Execution Core
516(2)
11.4.5.5 System Agent
518(1)
11.4.5.6 Intel Microarchitecture Code Name Ivy Bridge
519(1)
11.4.6 Ring Interconnect and Last Level Cache
519(1)
11.4.7 Data Prefetching
520(1)
11.4.7.1 Data Prefetch to L1 Data Cache
520(1)
11.4.7.2 Data Prefetch to L2 and Last Level Cache
521(1)
11.4.8 Branch-Prediction Examples
521(1)
11.4.8.1 Intel Microarchitecture Code Name Sandy Bridge
521(1)
11.4.8.2 Intel Core Microarchitecture
521(1)
11.4.8.3 Intel NetBurst Microarchitecture
522(5)
11.5 Summary
523(4)
Problems
523(1)
Bibliography
524(3)
Chapter 12 Advanced Architectures
527(3)
12.1 MISD
528(1)
12.2 SIMD
528(2)
12.2.1 Interconnection Networks for SIMD Architectures
530(1)
12.2.1.1 Terminology and Performance Measures
530(2)
12.2.1.2 Routing Protocols
532(1)
12.2.1.3 Static Topologies
533(4)
12.2.1.4 Dynamic Topologies
537(7)
12.3 MIMD
541(3)
12.3.1 MIMD Organization
544(1)
12.3.1.1 Shared-Memory Architecture
544(1)
12.3.1.2 Message-Passing Architecture
545(1)
12.3.1.3 Memory Organization
546(3)
12.3.2 Interconnection Networks for MIMD Architectures
548(1)
12.3.2.1 Bus Network
549(1)
12.3.2.2 Loop or Ring
550(1)
12.3.2.3 Mesh Network
551(1)
12.3.2.4 Hypercube Network
551(1)
12.3.2.5 Crossbar Network
551(1)
12.3.2.6 Multistage Networks
551(1)
12.3.2.7 Omega Network
552(10)
12.4 Cache Coherence
553(3)
12.5 Dataflow Architectures
556(2)
12.6 Systolic Architectures
558(1)
12.7 Example Systems
559(3)
12.7.1 Hyper-Threading Technology
560(2)
12.7.1.1 Microarchitecture Pipeline
562(1)
12.7.1.2 Front-End Pipeline
562(1)
12.7.1.3 Execution Core
562(1)
12.7.1.4 Retirement
562(15)
12.7.2 Intel SIMD Technology
563(3)
12.7.3 Cray XT4
566(5)
12.7.4 Cray XK7
571(3)
12.8 Summary
574(3)
Problems
574(1)
Bibliography
575(2)
Chapter 13 Embedded Systems
577(13)
13.1 Characteristics
578(1)
13.2 Software Architectures
579(2)
13.2.1 Simple Control Loop (Round Robin)
579(1)
13.2.2 Interrupt-Controlled Loop (Round Robin with Interrupts)
580(1)
13.2.3 Real-Time Operating System-Based Architectures
581(1)
13.3 Operating System
581(8)
13.3.1 Multitasking versus Concurrency
582(2)
13.3.2 Process Handling
584(1)
13.3.3 Synchronization Mechanisms
585(3)
13.3.4 Scheduling
588(1)
13.3.5 Real-Time Operating Systems
589(1)
13.4 Example Systems
589(1)
13.4.1 8051 Family of Microcontrollers
589(1)
13.4.1.1 DS89C450 Ultra-High-Speed Flash Microcontroller
590(1)
13.4.1.2 Internal Hardware Architecture
591(7)
13.4.2 ARM (Advanced RISC Machine) Microprocessor
597(1)
13.4.2.1 Internal Hardware Architecture
598(1)
13.4.2.2 ARM Three-Stage Pipeline Organization
598(1)
13.4.2.3 Single-Cycle Instruction Execution
598(2)
13.4.2.4 ARM Five-Stage Pipeline Organization
600(2)
13.4.2.5 Data Forwarding
602(1)
13.4.2.6 Programming Model
602(1)
13.4.2.7 Processor Modes
603(4)
13.5 Summary
605(2)
Problems
605(1)
Bibliography
606(1)
Chapter 14 Mobile Processors and System on Chip
607(5)
14.1 Apple iPhone 4S
609(2)
14.1.1 Hardware
610(1)
14.1.2 Software
610(1)
14.2 ARM v7-A Application Profile
611(1)
14.2.1 ARM Thumb-2 Instruction Set
611(1)
14.2.1.1 Exceptions
612(1)
14.2.1.2 Branch Instructions
612(1)
14.2.1.3 Data-Processing Instructions
612(1)
14.2.1.4 Load and Store Register Instructions
612(1)
14.2.1.5 Load and Store Multiple Instructions
612(11)
14.2.2 Thumb Execution Environment
613(1)
14.2.3 Advanced SIMD and VFP Extensions
613(1)
14.2.4 Security Extension Architecture
614(1)
14.2.5 Cortex-A8 Processor
614(2)
14.2.6 Cortex-A9 MPCore Processor
616(1)
14.2.7 Cortex-A15 Processor
617(3)
14.3 Raspberry Pi
620(1)
14.4 Summary
621(2)
Problems
621(1)
Bibliography
621(2)
Chapter 15 Computer Networks and Distributed Processing
623(26)
15.1 Computer Networks
624(8)
15.1.1 Network Architecture
625(1)
15.1.2 Network Reference Models
625(4)
15.1.3 Network Standardization
629(1)
15.1.4 Computer Network Types
629(2)
15.1.5 Internet and WWW
631(1)
15.2 Distributed Processing
632(7)
15.2.1 Processes and Threads
633(1)
15.2.2 Remote Procedure Call
634(1)
15.2.3 Process Synchronization and Mutual Exclusion
635(3)
15.2.4 Election Algorithms
638(1)
15.3 Grid Computing
639(3)
15.3.1 OGSA
640(2)
15.4 Cloud Computing
642(5)
15.4.1 Cloud Computing Characteristics
643(1)
15.4.2 Cloud Computing Service Models
644(1)
15.4.3 Cloud Computing Deployment Models
645(1)
15.4.4 Amazon EC2
645(2)
15.5 Summary
647(2)
Problems
647(1)
Bibliography
648(1)
Chapter 16 Performance Evaluation
649(14)
16.1 Performance Measures
650(3)
16.2 Cost Factor
653(1)
16.3 Benchmarks
654(4)
16.4 Code Optimization
658(2)
16.5 Summary
660(3)
Problems
660(1)
Bibliography
661(2)
Appendix A Details of Representative Integrated Circuits 663(22)
Appendix B Stack Implementation 685(2)
Index 687
Sajjan G. Shiva