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Computer Organization and Design: The Hardware/Software Interface 4th edition [Pehme köide]

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(Pardee Professor of Computer Science, Emeritus, University of California, Berkeley, USA), (Departments of Electrical Engineering and Computer Science, Stanford University, USA)
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The best-selling computer organization book is thoroughly updated to provide a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies, with examples highlighting the latest processor designs and benchmarking standards. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Sections on the ARM and x86 architectures are also included.

A companion CD provides a toolkit of simulators and compilers along with tutorials for using them, as well as advanced content for further study and a search utility for finding content on the CD and in the printed text.

  • Covers the revolutionary change from sequential to parallel computing, with a new chapter on parallelism and sections in every chapter highlighting parallel hardware and software topics.
  • Includes a new appendix by the Chief Scientist and the Director of Architecture of NVIDIA covering the emergence and importance of the modern GPU, describing in detail for the first time the highly parallel, highly multithreaded multiprocessor optimized for visual computing.
  • Describes a novel approach to measuring multicore performance--the "Roofline model"--with benchmarks and analysis for the AMD Opteron X4, Intel Xeon 5000, Sun UltraSPARC T2, and IBM Cell.
  • Includes new content on Flash memory and Virtual Machines.
  • Provides a large, stimulating set of new exercises, covering almost 200 pages.
  • Features the AMD Opteron X4 and Intel Nehalem as real-world examples throughout the book.
  • Updates all processor performance examples using the SPEC CPU2006 suite.


The best-selling computer organization book is thoroughly updated to provide a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies, with examples highlighting the latest processor designs and benchmarking standards. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Sections on the ARM and x86 architectures are also included.

All disc-based content for this title is now available on the Web.

  • Covers the revolutionary change from sequential to parallel computing, with a new chapter on parallelism and sections in every chapter highlighting parallel hardware and software topics.
  • Includes a new appendix by the Chief Scientist and the Director of Architecture of NVIDIA covering the emergence and importance of the modern GPU, describing in detail for the first time the highly parallel, highly multithreaded multiprocessor optimized for visual computing.
  • Describes a novel approach to measuring multicore performance--the "Roofline model"--with benchmarks and analysis for the AMD Opteron X4, Intel Xeon 5000, Sun UltraSPARC T2, and IBM Cell.
  • Includes new content on Flash memory and Virtual Machines.
  • Provides a large, stimulating set of new exercises, covering almost 200 pages.
  • Features the AMD Opteron X4 and Intel Nehalem as real-world examples throughout the book.
  • Updates all processor performance examples using the SPEC CPU2006 suite.

Arvustused

"Patterson and Hennessy have greatly improved what was already the gold standard of textbooks. In the rapidly-evolving field of computer architecture, they have woven an impressive number of recent case studies and contemporary issues into a framework of time-tested fundamentals." --Fred Chong, University of California, Santa Barbara

"The new coverage of multiprocessors and parallelism lives up to the standards of this well-written classic. It provides well-motivated, gentle introductions to the new topics, as well as many details and examples drawn from current hardware." --John Greiner, Rice University

Preface xv
Computer Abstractions and Technology
2(72)
Introduction
3(7)
Below Your Program
10(3)
Under the Covers
13(13)
Performance
26(13)
The Power Wall
39(2)
The Sea Change: The Switch from Uniprocessors to Multiprocessors
41(3)
Real Stuff: Manufacturing and Benchmarking the AMD Opteron X4
44(7)
Fallacies and Pitfalls
51(3)
Concluding Remarks
54(1)
Historical Perspective and Further Reading
55(1)
Exercises
56(18)
Instructions: Language of the Computer
74(148)
Introduction
76(1)
Operations of the Computer Hardware
77(3)
Operands of the Computer Hardware
80(7)
Signed and Unsigned Numbers
87(7)
Representing Instructions in the Computer
94(8)
Logical Operations
102(3)
Instructions for Making Decisions
105(7)
Supporting Procedures in Computer Hardware
112(10)
Communicating with People
122(6)
MIPS Addressing for 32-Bit Immediates and Addresses
128(9)
Parallelism and Instructions: Synchronization
137(2)
Translating and Starting a Program
139(10)
A C Sort Example to Put It All Together
149(8)
Arrays versus Pointers
157(4)
Advanced Material: Compiling C and Interpreting Java
161(1)
Real Stuff: ARM Instructions
161(4)
Real Stuff: x86 Instructions
165(9)
Fallacies and Pitfalls
174(2)
Concluding Remarks
176(3)
Historical Perspective and Further Reading
179(1)
Exercises
179(43)
Arithmetic for Computers
222(76)
Introduction
224(1)
Addition and Subtraction
224(6)
Multiplication
230(6)
Division
236(6)
Floating Point
242(28)
Parallelism and Computer Arithmetic: Associativity
270(2)
Real Stuff: Floating Point in the x86
272(3)
Fallacies and Pitfalls
275(5)
Concluding Remarks
280(3)
Historical Perspective and Further Reading
283(1)
Exercises
283(15)
The Processor
298(152)
Introduction
300(3)
Logic Design Conventions
303(4)
Building a Datapath
307(9)
A Simple Implementation Scheme
316(14)
An Overview of Pipelining
330(14)
Pipelined Datapath and Control
344(19)
Data Hazards: Forwarding versus Stalling
363(12)
Control Hazards
375(9)
Exceptions
384(7)
Parallelism and Advanced Instruction-Level Parallelism
391(13)
Real Stuff: the AMD Opteron X4 (Barcelona) Pipeline
404(2)
Advanced Topic: an Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
406(1)
Fallacies and Pitfalls
407(1)
Concluding Remarks
408(1)
Historical Perspective and Further Reading
409(1)
Exercises
409(41)
Large and Fast: Exploiting Memory Hierarchy
450(118)
Introduction
452(5)
The Basics of Caches
457(18)
Measuring and Improving Cache Performance
475(17)
Virtual Memory
492(26)
A Common Framework for Memory Hierarchies
518(7)
Virtual Machines
525(4)
Using a Finite-State Machine to Control a Simple Cache
529(5)
Parallelism and Memory Hierarchies: Cache Coherence
534(4)
Advanced Material: Implementing Cache Controllers
538(1)
Real Stuff: the AMD Opteron X4 (Barcelona) and Intel Nehalem Memory Hierarchies
539(4)
Fallacies and Pitfalls
543(4)
Concluding Remarks
547(1)
Historical Perspective and Further Reading
548(1)
Exercises
548(20)
Storage and Other I/O Topics
568(62)
Introduction
570(3)
Dependability, Reliability, and Availability
573(2)
Disk Storage
575(5)
Flash Storage
580(2)
Connecting Processors, Memory, and I/O Devices
582(4)
Interfacing I/O Devices to the Processor, Memory, and Operating System
586(10)
I/O Performance Measures: Examples from Disk and File Systems
596(2)
Designing an I/O System
598(1)
Parallelism and I/O: Redundant Arrays of Inexpensive Disks
599(7)
Real Stuff: Sun Fire x4150 Server
606(6)
Advanced Topics: Networks
612(1)
Fallacies and Pitfalls
613(4)
Concluding Remarks
617(1)
Historical Perspective and Further Reading
618(1)
Exercises
619(11)
Multicores, Multiprocessors, and Clusters
630(2)
Introduction
632(2)
The Difficulty of Creating Parallel Processing Programs
634(4)
Shared Memory Multiprocessors
638(3)
Clusters and Other Message-Passing Multiprocessors
641(4)
Hardware Multithreading
645(3)
SISD, MIMD, SIMD, SPMD, and Vector
648(6)
Introduction to Graphics Processing Units
654(6)
Introduction to Multiprocessor Network Topologies
660(4)
Multiprocessor Benchmarks
664(3)
Roofline: A Simple Performance Model
667(8)
Real Stuff: Benchmarking Four Multicores Using the Roofline Model
675(9)
Fallacies and Pitfalls
684(2)
Concluding Remarks
686(2)
Historical Perspective and Further Reading
688(1)
Exercises
688
Appendices
Graphics and Computing GPUs
2(1)
Introduction
3(4)
GPU System Architectures
7(5)
Programming GPUs
12(13)
Multithreaded Multiprocessor Architecture
25(11)
Parallel Memory System
36(5)
Floating Point Arithmetic
41(5)
Real Stuff: The NVIDIA GeForce 8800
46(9)
Real Stuff: Mapping Applications to GPUs
55(17)
Fallacies and Pitfalls
72(4)
Concluding Remarks
76(1)
Historical Perspective and Further Reading
77
Assemblers, Linkers, and the SPIM Simulator
2
Introduction
3(7)
Assemblers
10(8)
Linkers
18(1)
Loading
19(1)
Memory Usage
20(2)
Procedure Call Convention
22(11)
Exceptions and Interrupts
33(5)
Input and Output
38(2)
SPIM
40(5)
MIPS R2000 Assembly Language
45(36)
Concluding Remarks
81(1)
Exercises
82
Index 1(1)
The Basics of Logic Design
2(1)
Introduction
3(1)
Gates, Truth Tables, and Logic Equations
4(5)
Combinational Logic
9(11)
Using a Hardware Description Language
20(6)
Constructing a Basic Arithmetic Logic Unit
26(12)
Faster Addition: Carry Lookahead
38(10)
Clocks
48(2)
Memory Elements: Flip-Flops, Latches, and Registers
50(8)
Memory Elements: SRAMs and DRAMs
58(9)
Finite-State Machines
67(5)
Timing Methodologies
72(6)
Field Programmable Devices
78(1)
Concluding Remarks
79(1)
Exercises
80
Mapping Control to Hardware
2(1)
Introduction
3(1)
Implementing Combinational Control Units
4(4)
Implementing Finite-State Machine Control
8(14)
Implementing the Next-State Function with a Sequencer
22(6)
Translating a Microprogram to Hardware
28(4)
Concluding Remarks
32(1)
Exercises
33
A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
2
Introduction
3(2)
Addressing Modes and Instruction Formats
5(4)
Instructions: The MIPS Core Subset
9(7)
Instructions: Multimedia Extensions of the Desktop/Server RISCs
16(3)
Instructions: Digital Signal-Processing Extensions of the Embedded RISCs
19(1)
Instructions: Common Extensions to MIPS Core
20(5)
Instructions Unique to MIPS-64
25(2)
Instructions Unique to Alpha
27(2)
Instructions Unique to SPARC v.9
29(3)
Instructions Unique to PowerPC
32(2)
Instructions Unique to PA-RISC 2.0
34(2)
Instructions Unique to ARM
36(2)
Instructions Unique to Thumb
38(1)
Instructions Unique to SuperH
39(1)
Instructions Unique to M32R
40(1)
Instructions Unique to MIPS-16
40(3)
Concluding Remarks
43
Glossary 1(1)
Further Reading 1
ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates. ACM named David A. Patterson a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. David A. Patterson is the Pardee Chair of Computer Science, Emeritus at the University of California Berkeley. His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.