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Computer Organization and Design MIPS Edition: The Hardware/Software Interface 6th edition [Pehme köide]

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(Departments of Electrical Engineering and Computer Science, Stanford University, USA), (Pardee Professor of Computer Science, Emeritus, University of California, Berkeley, USA)
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Computer Organization and Design MIPS Edition: The Hardware/Software Interface 6th editionSuurem pilt
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Computer Organization and Design: The Hardware/Software Interface, Sixth Edition, the leading, award-winning textbook from Patterson and Hennessy used by more than 40,000 students per year, continues to present the most comprehensive and readable introduction to this core computer science topic. Improvements to this new release include new sections in each chapter on Domain Specific Architectures (DSA) and updates on all real-world examples that keep it fresh and relevant for a new generation of students.
  • Covers parallelism in-depth, with examples and content highlighting parallel hardware and software topics
  • Includes new sections in each chapter on Domain Specific Architectures (DSA)
  • Discusses and highlights the "Eight Great Ideas" of computer architecture, including Performance via Parallelism, Performance via Pipelining, Performance via Prediction, Design for Moore's Law, Hierarchy of Memories, Abstraction to Simplify Design, Make the Common Case Fast and Dependability via Redundancy
Preface xv
1 Computer Abstractions and Technology 2(64)
1.1 Introduction
3(7)
1.2 Seven Great Ideas in Computer Architecture
10(3)
1.3 Below Your Program
13(3)
1.4 Under the Covers
16(8)
1.5 Technologies for Building Processors and Memory
24(4)
1.6 Performance
28(12)
1.7 The Power Wall
40(3)
1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors
43(3)
1.9 Real Stuff: Benchmarking the Intel Core i7
46(3)
1.10 Going Faster: Matrix Multiply in Python
49(1)
1.11 Fallacies and Pitfalls
50(3)
1.12 Concluding Remarks
53(2)
1.13 Historical Perspective and Further Reading
55(1)
1.14 Self-Study
55(4)
1.15 Exercises
59(7)
2 Instructions: Language of the Computer 66(120)
2.1 Introduction
68(1)
2.2 Operations of the Computer Hardware
69(3)
2.3 Operands of the Computer Hardware
72(7)
2.4 Signed and Unsigned Numbers
79(7)
2.5 Representing Instructions in the Computer
86(7)
2.6 Logical Operations
93(3)
2.7 Instructions for Making Decisions
96(6)
2.8 Supporting Procedures in Computer Hardware
102(10)
2.9 Communicating with People
112(6)
2.10 MIPS Addressing for 32-Bit Immediates and Addresses
118(9)
2.11 Parallelism and Instructions: Synchronization
127(2)
2.12 Translating and Starting a Program
129(9)
2.13 A C Sort Example to Put It All Together
138(9)
2.14 Arrays versus Pointers
147(4)
2.15 Advanced Material: Compiling C and Interpreting Java
151(1)
2.16 Real Stuff: ARMv7 (32-bit) Instructions
151(4)
2.17 Real Stuff: ARMv8 (64-bit) Instructions
155(1)
2.18 Real Stuff: RISC-V Instructions
156(1)
2.19 Real Stuff: x86 Instructions
157(9)
2.20 Going Faster: Matrix Multiply in C
166(1)
2.21 Fallacies and Pitfalls
167(2)
2.22 Concluding Remarks
169(3)
2.23 Historical Perspective and Further Reading
172(1)
2.24 Self Study
172(3)
2.25 Exercises
175(11)
3 Arithmetic for Computers 186(68)
3.1 Introduction
188(1)
3.2 Addition and Subtraction
188(5)
3.3 Multiplication
193(6)
3.4 Division
199(7)
3.5 Floating Point
206(26)
3.6 Parallelism and Computer Arithmetic: Subword Parallelism
232(2)
3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x86
234(1)
3.8 Going Faster: Subword Parallelism and Matrix Multiply
235(2)
3.9 Fallacies and Pitfalls
237(4)
3.10 Concluding Remarks
241(4)
3.11 Historical Perspective and Further Reading
245(1)
3.12 Self Study
245(3)
3.13 Exercises
248(6)
4 The Processor 254(136)
4.1 Introduction
256(4)
4.2 Logic Design Conventions
260(3)
4.3 Building a Datapath
263(8)
4.4 A Simple Implementation Scheme
271(13)
4.5 A Multicycle Implementation
284(1)
4.6 An Overview of Pipelining
285(13)
4.7 Pipelined Datapath and Control
298(17)
4.8 Data Hazards: Forwarding versus Stalling
315(13)
4.9 Control Hazards
328(9)
4.10 Exceptions
337(7)
4.11 Parallelism via Instructions
344(14)
4.12 Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53
358(8)
4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply
366(2)
4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
368(1)
4.15 Fallacies and Pitfalls
369(1)
4.16 Concluding Remarks
370(1)
4.17 Historical Perspective and Further Reading
371(1)
4.18 Self-Study
371(1)
4.19 Exercises
372(18)
5 Large and Fast: Exploiting Memory Hierarchy 390(134)
5.1 Introduction
392(4)
5.2 Memory Technologies
396(5)
5.3 The Basics of Caches
401(15)
5.4 Measuring and Improving Cache Performance
416(20)
5.5 Dependable Memory Hierarchy
436(6)
5.6 Virtual Machines
442(4)
5.7 Virtual Memory
446(26)
5.8 A Common Framework for Memory Hierarchy
472(7)
5.9 Using a Finite-State Machine to Control a Simple Cache
479(5)
5.10 Parallelism and Memory Hierarchies: Cache Coherence
484(4)
5.11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
488(1)
5.12 Advanced Material: Implementing Cache Controllers
488(1)
5.13 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies
489(5)
5.14 Going Faster: Cache Blocking and Matrix Multiply
494(2)
5.15 Fallacies and Pitfalls
496(4)
5.16 Concluding Remarks
500(1)
5.17 Historical Perspective and Further Reading
501(1)
5.18 Self-Study
501(5)
5.19 Exercises
506(18)
6 Parallel Processors from Client to Cloud 524
6.1 Introduction
526(2)
6.2 The Difficulty of Creating Parallel Processing Programs
528(5)
6.3 SISD, MIMD, SIMD, SPMD, and Vector
533(7)
6.4 Hardware Multithreading
540(3)
6.5 Multicore and Other Shared Memory Multiprocessors
543(5)
6.6 Introduction to Graphics Processing Units
548(7)
6.7 Domain Specific Architectures
555(3)
6.8 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors
558(5)
6.9 Introduction to Multiprocessor Network Topologies
563(3)
6.10 Communicating to the Outside World: Cluster Networking
566(1)
6.11 Multiprocessor Benchmarks and Performance Models
567(10)
6.12 Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster
577(9)
6.13 Going Faster: Multiple Processors and Matrix Multiply
586(3)
6.14 Fallacies and Pitfalls
589(3)
6.15 Concluding Remarks
592(2)
6.16 Historical Perspective and Further Reading
594(1)
6.17 Self Study
594(2)
6.18 Exercises
596
Appendices
A Assemblers, Linkers, and the SPIM Simulator
A-610
A.1 Introduction
A-611
A.2 Assemblers
A-618
A.3 Linkers
A-626
A.4 Loading
A-627
A.5 Memory Usage
A-628
A.6 Procedure Call Convention
A-630
A.7 Exceptions and Interrupts
A-641
A.8 Input and Output
A-646
A.9 SPIM
A-648
A.10 MIPS R2000 Assembly Language
A-653
A.11 Concluding Remarks
A-689
A.12 Exercises
A-690
B The Basics of Logic Design
B-692
B.1 Introduction
B-693
B.2 Gates, Truth Tables, and Logic Equations
B-694
B.3 Combinational Logic
B-699
B.4 Using a Hardware Description Language
B-710
B.5 Constructing a Basic Arithmetic Logic Unit
B-716
B.6 Faster Addition: Carry Lookahead
B-728
B.7 Clocks
B-738
B.8 Memory Elements: Flip-Flops, Latches, and Registers
B-740
B.9 Memory Elements: SRAMs and DRAMs
B-748
B.10 Finite-State Machines
B-757
B.11 Timing Methodologies
B-762
B.12 Field Programmable Devices
B-768
B.13 Concluding Remarks
B-769
B.14 Exercises
B-770
Index I-1
ACM named David A. Patterson a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. David A. Patterson is the Pardee Chair of Computer Science, Emeritus at the University of California Berkeley. His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH. ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates.