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Computer Systems: Digital Design, Fundamentals of Computer Architecture and ARM Assembly Language Second Edition 2022 [Kõva köide]

  • Formaat: Hardback, 296 pages, kõrgus x laius: 235x155 mm, kaal: 641 g, 297 Illustrations, color; 162 Illustrations, black and white; XVIII, 296 p. 459 illus., 297 illus. in color., 1 Hardback
  • Ilmumisaeg: 17-Mar-2022
  • Kirjastus: Springer Nature Switzerland AG
  • ISBN-10: 3030934489
  • ISBN-13: 9783030934484
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Computer Systems: Digital Design, Fundamentals of Computer Architecture and ARM Assembly Language Second Edition 2022Suurem pilt
  • Formaat: Hardback, 296 pages, kõrgus x laius: 235x155 mm, kaal: 641 g, 297 Illustrations, color; 162 Illustrations, black and white; XVIII, 296 p. 459 illus., 297 illus. in color., 1 Hardback
  • Ilmumisaeg: 17-Mar-2022
  • Kirjastus: Springer Nature Switzerland AG
  • ISBN-10: 3030934489
  • ISBN-13: 9783030934484
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783030934484.html
Märksõnad:

This updated textbook covers digital design, fundamentals of computer architecture, and ARM assembly language. The book starts by introducing computer abstraction, basic number systems, character coding, basic knowledge in digital design, and components of a computer. The book goes on to discuss information representation in computing, Boolean algebra and logic gates, and sequential logic. The book also presents introduction to computer architecture, Cache mapping methods, and virtual memory.

The author also covers ARM architecture, ARM instructions, ARM assembly language using Keil development tools, and bitwise control structure using C and ARM assembly language. The book includes a set of laboratory experiments related to digital design using Logisim software and ARM assembly language programming using Keil development tools. In addition, each chapter features objectives, summaries, key terms, review questions, and problems.

1 Signals and Number Systems
1(32)
1.1 Introduction
1(2)
1.1.1 CPU
2(1)
1.2 Historical Development of the Computer
3(1)
1.3 Hardware and Software Components of a Computer
3(1)
1.4 Types of Computers
4(1)
1.5 Analog Signals
5(2)
1.5.1 Characteristics of an Analog Signal
6(1)
1.6 Digital Signals
7(1)
1.7 Number System
8(5)
1.7.1 Converting from Binary to Decimal
9(1)
1.7.2 Converting from Decimal Integer to Binary
10(1)
1.7.3 Converting Decimal Fraction to Binary
10(1)
1.7.4 Converting from Hex to Binary
11(2)
1.7.5 Binary Addition
13(1)
1.8 Complement and Two's Complement
13(2)
1.8.1 Subtraction of Unsigned Number Using Two's Complement
14(1)
1.9 Unsigned, Signed Magnitude, and Signed Two's Complement Binary Number
15(1)
1.9.1 Unsigned Number
15(1)
1.9.2 Signed Magnitude Number
15(1)
1.9.3 Signed Two's Complement
15(1)
1.10 Binary Addition Using Signed Two's Complement
16(1)
1.11 Floating Point Representation
17(2)
1.11.1 Single and Double Precision Representations of Floating Point
18(1)
1.12 Binary-Coded Decimal (BCD)
19(1)
1.13 Coding Schemes
20(3)
1.13.1 ASCII Code
20(1)
1.13.2 Universal Code or Unicode
20(3)
1.14 Parity Bit
23(1)
1.14.1 Even Parity
24(1)
1.14.2 Odd Parity
24(1)
1.15 Clock
24(1)
1.16 Transmission Modes
25(1)
1.16.1 Asynchronous Transmission
25(1)
1.16.2 Synchronous Transmission
26(1)
1.17 Transmission Methods
26(1)
1.17.1 Serial Transmission
27(1)
1.17.2 Parallel Transmission
27(1)
1.18 Summary
27(6)
2 Boolean Logics and Logic Gates
33(18)
2.1 Introduction
33(1)
2.2 Boolean Logics and Logic Gates
33(6)
2.2.1 AND Logic
34(1)
2.2.2 OR Logic
35(1)
2.2.3 NOT Logic
35(1)
2.2.4 NAND Gate
36(1)
2.2.5 NOR Gate
36(1)
2.2.6 Exclusive OR Gate
37(1)
2.2.7 Exclusive NOR Gate
37(1)
2.2.8 Tri-State Device
37(1)
2.2.9 Multiple Inputs Logic Gates
38(1)
2.3 Integrated Circuit (IC) Classifications
39(2)
2.3.1 Small-Scale Integration (SSI)
40(1)
2.3.2 Integrated Circuit Pins Numbering
40(1)
2.3.3 Medium-Scale Integration (MSI)
41(1)
2.3.4 Large-Scale Integration (LSI)
41(1)
2.3.5 Very-Large-Scale Integration (VLSI)
41(1)
2.4 Boolean Algebra Theorems
41(3)
2.4.1 Distributive Theorem
42(1)
2.4.2 De Morgan's Theorem I
43(1)
2.4.3 De Morgan's Theorem II
43(1)
2.4.4 Commutative Law
44(1)
2.4.5 Associative Law
44(1)
2.4.6 More Theorems
44(1)
2.5 Boolean Function
44(2)
2.5.1 Complement of a Function
45(1)
2.6 Summary
46(5)
Problems
46(5)
3 Minterms, Maxterms, Karnaugh Map (K-Map), and Universal Gates
51(24)
3.1 Introduction
51(1)
3.2 Minterms
51(4)
3.2.1 Application of Minterms
52(1)
3.2.2 Three-Variable Minterms
52(3)
3.3 Maxterms
55(1)
3.4 Karnaugh Map (K-Map)
56(6)
3.4.1 Three-Variable Map
58(3)
3.4.2 Four-Variable K-Map
61(1)
3.5 Sum of Products (SOP) and Product of Sums (POS)
62(2)
3.6 Don't Care Conditions
64(2)
3.7 Universal Gates
66(3)
3.7.1 Using NAND Gates
66(1)
3.7.2 Using NOR Gates
66(1)
3.7.3 Implementation of Logic Functions Using NAND Gates or NOR Gates Only
67(1)
3.7.4 Using NAND Gates
68(1)
3.7.5 Using NOR Gates
68(1)
3.8 Summary
69(6)
Problems
70(5)
4 Combinational Logic
75(28)
4.1 Introduction
75(1)
4.2 Analysis of Combinational Logic
76(1)
4.3 Design of Combinational Logic
77(2)
4.3.1 Solution
78(1)
4.4 Decoder
79(1)
4.4.1 Implementing a Function Using a Decoder
79(1)
4.5 Encoder
80(1)
4.6 Multiplexer (MUX)
81(7)
4.6.1 Designing Large Multiplexer Using Smaller Multiplexers
85(1)
4.6.2 Implementing Functions Using Multiplexer
86(2)
4.7 Half Adder, Full Adder, Binary Adder, and Subtractor
88(5)
4.7.1 Full Adder (FA)
90(1)
4.7.2 4-Bit Binary Adder
91(2)
4.7.3 Subtractor
93(1)
4.8 ALU (Arithmetic Logic Unit)
93(2)
4.9 Seven-Segment Display
95(2)
4.10 Summary
97(6)
Problems
98(5)
5 Synchronous Sequential Logic
103(18)
5.1 Introduction
103(1)
5.2 S-R Latch
103(2)
5.2.1 S-R Latch Operation
104(1)
5.3 D Flip-Flop
105(1)
5.4 J-K Flip-Flop
106(1)
5.5 T Flip-Flop
107(1)
5.6 Register
107(3)
5.6.1 Shift Register
108(1)
5.6.2 Barrel Shifter
109(1)
5.7 Frequency Divider Using J-K Flip-Flop
110(1)
5.8 Analysis of Sequential Logic
110(2)
5.9 State Diagram
112(1)
5.9.1 D Flip-Flop State Diagram
112(1)
5.10 Flip-Flop Excitation Table
113(2)
5.10.1 D Flip-Flop Excitation Table
113(1)
5.10.2 Excitation Table Operation
114(1)
5.10.3 J-K Flip-Flop Excitation Table
114(1)
5.10.4 T Flip-Flop Excitation Table
114(1)
5.11 Counter
115(1)
5.12 Summary
116(5)
Problems
118(3)
6 Introduction to Computer Architecture
121(26)
6.1 Introduction
121(1)
6.1.1 Abstract Representation of Computer Architecture
121(1)
6.2 Components of a Microcomputer
122(5)
6.2.1 Central Processing Unit (CPU)
123(1)
6.2.2 CPU Buses
124(1)
6.2.3 Memory
125(1)
6.2.4 Serial Input/Output
126(1)
6.2.5 Direct Memory Access (DMA)
126(1)
6.2.6 Programmable I/O Interrupt
126(1)
6.2.7 32-Bit Versus 64-Bit CPU
127(1)
6.3 CPU Technology
127(2)
6.3.1 CISC (Complex Instruction Set Computer)
127(1)
6.3.2 RISC
128(1)
6.4 CPU Architecture
129(1)
6.4.1 Von Neumann Architecture
129(1)
6.4.2 Harvard Architecture
129(1)
6.5 Intel Microprocessor Family
130(1)
6.5.1 Upward Compatibility
130(1)
6.6 Multicore Processors
131(2)
6.7 CPU Instruction Execution Steps
133(1)
6.7.1 Pipelining
133(1)
6.8 Disk Controller
134(1)
6.9 Microcomputer Bus
134(6)
6.9.1 ISA Bus
134(1)
6.9.2 MicroChannel Architecture Bus
135(1)
6.9.3 EISA Bus
135(1)
6.9.4 VESA Bus
135(1)
6.9.5 PCI Bus
135(1)
6.9.6 Universal Serial BUS (USB)
136(1)
6.9.7 USB Architecture
136(3)
6.9.8 PCI Express Bus
139(1)
6.10 Fire Wire
140(2)
6.10.1 HDMI (High-Definition Multimedia Interface)
141(1)
6.11 Summary
142(5)
Review Questions
143(4)
7 Memory
147(28)
7.1 Introduction
147(1)
7.2 Memory
147(5)
7.2.1 RAM
148(3)
7.2.2 DRAM Packaging
151(1)
7.2.3 ROM (Read-Only Memory)
151(1)
7.2.4 Memory Access Time
152(1)
7.3 Hard Disk
152(2)
7.3.1 Disk Characteristics
152(2)
7.3.2 Cluster
154(1)
7.3.3 Disk File System
154(1)
7.4 Solid-State Drive (SSD)
154(1)
7.5 Memory Hierarchy
155(20)
7.5.1 Cache Memory
156(1)
7.5.2 Cache Terminology
156(1)
7.5.3 Cache Memory Mapping Methods
157(1)
7.5.4 Direct Mapping
157(4)
7.5.5 Set Associative Mapping
161(1)
7.5.6 Replacement Method
162(1)
7.5.7 Fully Associative Mapping
163(1)
7.5.8 Cache Update Methods
163(1)
7.5.9 Effective Access Time (EAT) of Memory
164(1)
7.5.10 Virtual Memory
164(1)
7.5.11 Memory Organization of a Computer
165(3)
Questions and Problems
168(1)
Problems
169(6)
8 Assembly Language and ARM Instructions Part 1
175(22)
8.1 Introduction
175(1)
8.2 Instruction Set Architecture (ISA)
176(1)
8.2.1 Classification of Instruction Based on Number of Operands
176(1)
8.3 ARM Processor Architecture
177(3)
8.3.1 Instruction Decoder and Logic Control
178(1)
8.3.2 Address Register
178(1)
8.3.3 Address Increment
178(1)
8.3.4 Register Bank
178(1)
8.3.5 Barrel Shifter
179(1)
8.3.6 ALU
179(1)
8.3.7 Write Data Register
180(1)
8.3.8 Read Data Register
180(1)
8.3.9 ARM Operation Mode
180(1)
8.4 ARM Registers
180(2)
8.4.1 Current Program Status Register (CPSR)
180(1)
8.4.2 Flag Bits
181(1)
8.4.3 Control Bits
181(1)
8.5 ARM Instructions
182(8)
8.5.1 Data Processing Instructions
182(1)
8.5.2 Compare and Test Instructions
183(2)
8.5.3 Register Swap Instructions (MOV and MVN)
185(1)
8.5.4 Shift and Rotate Instructions
186(2)
8.5.5 ARM Unconditional Instructions and Conditional Instructions
188(2)
8.6 Stack Operation and Instructions
190(1)
8.7 Branch (B) and Branch with Link Instruction (BL)
191(1)
8.8 Multiply (MUL) and Multiply-Accumulate (MLA) Instructions
192(1)
8.9 Summary
192(5)
Problems and Questions
193(4)
9 ARM Assembly Language Programming Using Keil Development Tools
197(16)
9.1 Introduction
197(1)
9.2 Keil Development Tools for ARM Assembly
198(7)
9.2.1 Assembling a Program
202(2)
9.2.2 Running the Debugger/Simulator
204(1)
9.3 Program Template
205(1)
9.4 Programming Rules
205(1)
9.4.1 CASE Rules
205(1)
9.4.2 Comments
205(1)
9.5 Data Representation and Memory
206(2)
9.6 Directives
208(2)
9.6.1 Data Directive
208(2)
9.7 Memory in uVision v5
210(1)
9.8 Summary
211(2)
Questions and Problems
212(1)
10 ARM Instructions Part II and Instruction Formats
213(18)
10.1 Introduction
213(1)
10.2 ARM Data Transfer Instructions
213(2)
10.2.1 ARM Pseudo Instructions
214(1)
10.2.2 Store Instructions (STR)
215(1)
10.3 ARM Addressing Mode
215(4)
10.3.1 Immediate Addressing
216(1)
10.3.2 Pre-indexed
216(1)
10.3.3 Pre-indexed with Write Back
217(1)
10.3.4 Post-index Addressing
218(1)
10.4 Swap Memory and Register (SWAP)
219(1)
10.5 Storing Data Using Keil μ Vision 5
219(1)
10.6 Bits Field Instructions
220(1)
10.7 ARM Instruction Formats
221(5)
10.7.1 ARM Data Processing Instruction Format
221(3)
10.7.2 B and BL Instruction Format
224(1)
10.7.3 Multiply Instruction Format
224(1)
10.7.4 Data Transfer Instructions (LDRB, LDR, STRB, and STR)
225(1)
10.7.5 Data Transfer Half Word and Signed Number (LDRH, STRH, LDRSB, LDRSH)
225(1)
10.7.6 Swap Memory and Register (SWAP)
226(1)
10.8 Summary
226(5)
Problems
227(4)
11 Bitwise and Control Structures Used for Programming with C and ARM Assembly Language
231(16)
11.1 Introduction
231(3)
11.1.1 C Bitwise Operations
231(3)
11.2 Control Structures
234(8)
11.2.1 If-Then Structure
234(1)
11.2.2 If-Then-Else Structure
235(1)
11.2.3 While Loop Structure
236(1)
11.2.4 For Loop Structure
237(1)
11.2.5 Switch Structure
238(4)
11.3 ARM Memory Map
242(2)
11.3.1 Introduction
242(2)
11.4 Local and Global Variables
244(2)
11.5 Summary
246(1)
Problems
246(1)
Appendix A List of Digital Design Laboratory Experiments Using LOGISIM 247(2)
Appendix B Solution to the Even Problems 249(38)
Bibliography 287(4)
Index 291
Dr. Ata Elahi is a professor of Computer Science at Southern Connecticut State University. Dr. Elahi received his Ph.D. in Electrical Engineering from Mississippi State University in 1982. He is the author of the following textbooks:  Computer Systems, ARM Assembly Language with Hardware Experiments, published by Springer 2018 and 2015; ZigBee Wireless Sensor and Control Network, published by Prentice Hall, 2010; Data, Network & Internet Communications Technology, published by Thomson Learning 2006; Network Communication Technology, published by Delmar Thomson Learning 2001.