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Crystal Growth and Evaluation of Silicon for VLSI and ULSI [Kõva köide]

(Central Electronics Engineering Research Institute (CEERI), Pilani, India)
  • Formaat: Hardback, 430 pages, kõrgus x laius: 254x178 mm, kaal: 952 g, 23 Tables, black and white; 264 Illustrations, black and white
  • Ilmumisaeg: 08-Dec-2014
  • Kirjastus: CRC Press Inc
  • ISBN-10: 1482232812
  • ISBN-13: 9781482232813
Teised raamatud teemal:
  • Formaat: Hardback, 430 pages, kõrgus x laius: 254x178 mm, kaal: 952 g, 23 Tables, black and white; 264 Illustrations, black and white
  • Ilmumisaeg: 08-Dec-2014
  • Kirjastus: CRC Press Inc
  • ISBN-10: 1482232812
  • ISBN-13: 9781482232813
Teised raamatud teemal:
Silicon, as a single-crystal semiconductor, has sparked a revolution in the field of electronics and touched nearly every field of science and technology. Though available abundantly as silica and in various other forms in nature, silicon is difficult to separate from its chemical compounds because of its reactivity. As a solid, silicon is chemically inert and stable, but growing it as a single crystal creates many technological challenges.Crystal Growth and Evaluation of Silicon for VLSI and ULSI is one of the first books to cover the systematic growth of silicon single crystals and the complete evaluation of silicon, from sand to useful wafers for device fabrication. Written for engineers and researchers working in semiconductor fabrication industries, this practical text:Describes different techniques used to grow silicon single crystalsExplains how grown single-crystal ingots become a complete silicon wafer for integrated-circuit fabricationReviews different methods to evaluate silicon wafers to determine suitability for device applicationsAnalyzes silicon wafers in terms of resistivity and impurity concentration mappingExamines the effect of intentional and unintentional impuritiesExplores the defects found in regular silicon-crystal latticeDiscusses silicon wafer preparation for VLSI and ULSI processingCrystal Growth and Evaluation of Silicon for VLSI and ULSI is an essential reference for different approaches to the selection of the basic silicon-containing compound, separation of silicon as metallurgical-grade pure silicon, subsequent purification, single-crystal growth, and defects and evaluation of the deviations within the grown crystals.
Preface xiii
About the Author xvii
1 Introduction 1(26)
1.1 Silicon: The Semiconductor
2(1)
1.2 Why Single Crystals
2(2)
1.3 Revolution in Integrated Circuit Fabrication Technology and the Art of Device Miniaturization
4(2)
1.4 Use of Silicon as a Semiconductor
6(5)
1.5 Silicon Devices for Boolean Applications
11(1)
1.6 Integration of Silicon Devices and the Art of Circuit Miniaturization
12(6)
1.7 MOS and CMOS Devices for Digital Applications
18(1)
1.8 LSI, VLSI, and ULSI Circuits and Applications
18(2)
1.9 Silicon for MEMS Applications
20(3)
1.10 Summary
23(1)
References
23(4)
2 Silicon: The Key Material for Integrated Circuit Fabrication Technology 27(18)
2.1 Introduction
27(1)
2.2 Preparation of Raw Silicon Material
28(1)
2.3 Metallurgical-Grade Silicon
29(2)
2.4 Purification of Metallurgical-Grade Silicon
31(6)
2.5 Ultra-High Pure Silicon for Electronics Applications
37(1)
2.6 Polycrystalline Silicon Feed for Crystal Growth
37(4)
2.7 Summary
41(1)
References
41(4)
3 Importance of Single Crystals for Integrated Circuit Fabrication 45(14)
3.1 Introduction
45(1)
3.2 Crystal Structures
45(2)
3.2.1 Different Crystal Structures in Nature
47(1)
3.2.2 Cubic Structures
47(1)
3.3 Diamond Crystal Structure
47(1)
3.3.1 Silicon Crystal Structure
47(1)
3.3.2 Silicon Crystals and Atomic Packing Factors
48(1)
3.4 Crystal Order and Perfection
48(2)
3.5 Crystal Orientations and Planes
50(4)
3.6 Influence of Dopants and Impurities in Silicon Crystals
54(4)
3.7 Summary
58(1)
References
58(1)
4 Different Techniques for Growing Single-Crystal Silicon 59(98)
4.1 Introduction
59(1)
4.2 Bridgman Crystal Growth Technique
60(1)
4.3 Czochralski Crystal Growth/Pulling Technique
60(64)
4.3.1 Crucible Choice for Molten Silicon
64(8)
4.3.2 Chamber Temperature Profile
72(5)
4.3.3 Seed Selection for Crystal Pulling
77(5)
4.3.4 Environmental and Ambient Control in the Crystal Chamber
82(2)
4.3.5 Crystal Pull Rate and Seed/Crucible Rotation
84(10)
4.3.6 Dopant Addition for Growing Doped Crystals
94(6)
4.3.6.1 Boron
94(1)
4.3.6.2 Phosphorus
95(1)
4.3.6.3 Arsenic
96(1)
4.3.6.4 Gallium
96(1)
4.3.6.5 Nitrogen
96(1)
4.3.6.6 Antimony
97(2)
4.3.6.7 Germanium
99(1)
4.3.7 Methods for Continuous Czochralski Crystal Growth
100(2)
4.3.8 Impurity Segregation Between Liquid and Grown Silicon Crystals
102(5)
4.3.9 Crystal Growth Striations
107(1)
4.3.10 Use of a Magnetic Field in the Czochralski Growth Technique
108(9)
4.3.11 Large-Area Silicon Crystals for VLSI and ULSI Applications
117(5)
4.3.12 Post-Growth Thermal Gradient and Crystal Cooling after Pull-Out
122(2)
4.4 Float-Zone Crystal Growth Technique
124(11)
4.4.1 Seed Selection
125(1)
4.4.2 Environment and Chamber Ambient Control
125(1)
4.4.3 Heating Mechanisms and RF Coil Shape
125(1)
4.4.4 Crystal Growth Rate and Seed Rotation
126(2)
4.4.5 Dopant Distribution in Growing Crystals
128(2)
4.4.6 Impurity Segregation between Liquid and Grown Silicon Crystals
130(1)
4.4.7 Use of Magnetic Fields for Float-Zone Growth
130(1)
4.4.8 Large Area Silicon Crystals and Limitations of Shape and Size
131(4)
4.4.9 Thermal Gradient and Post-Growth Crystal Cooling
135(1)
4.5 Zone Refining of Single-Crystal Silicon
135(1)
4.6 Other Silicon Crystalline Structures and Growth Techniques
136(2)
4.6.1 Silicon Ribbons
136(1)
4.6.2 Silicon Sheets
137(1)
4.6.3 Silicon Whiskers and Fibers
137(1)
4.6.4 Silicon in Circular and Spherical Shapes
137(1)
4.6.5 Silicon Hollow Tubes
138(1)
4.6.6 Casting of Polycrystalline Silicon for Photovoltaic Applications
138(1)
4.7 Summary
138(1)
References
139(18)
5 From Silicon Ingots to Silicon Wafers 157(18)
5.1 Introduction
157(1)
5.2 Radial Resistivity Measurements
157(1)
5.3 Boule Formation, Identification of Crystal Orientation, and Flats
158(4)
5.4 Ingot Slicing
162(2)
5.5 Mechanical Lapping of Wafer Slices
164(3)
5.6 Edge Profiling of Slices
167(1)
5.7 Chemical Etching and Mechanical Damage Removal
167(1)
5.8 Chemimechanical Polishing for Planar Wafers
168(2)
5.9 Surface Roughness and Overall Wafer Topography
170(1)
5.10 Megasonic Cleaning
170(1)
5.11 Final Cleaning and Inspection
171(1)
5.12 Summary
171(1)
References
172(3)
6 Evaluation of Silicon Wafers 175(50)
6.1 Introduction
175(1)
6.2 Acoustic Laser Probing Technique
175(3)
6.3 Atomic-Force Microscope Studies on Surfaces
178(1)
6.4 Auger Electron Spectroscopic Studies
178(3)
6.5 Chemical Staining and Etching Techniques
181(3)
6.6 Contactless Characterization
184(1)
6.7 Deep-Level Transient Spectroscopy
185(2)
6.8 Defect Decoration by Metals
187(1)
6.9 Electron Beam and High-Energy Electron Diffraction Studies
188(1)
6.10 Flame Emission Spectrometry
188(1)
6.11 Four-Point Probe Technique for Resistivity Measurement and Mapping
189(2)
6.12 Fourier Transform Infrared Spectroscopy Measurements for Impurity Identification
191(4)
6.13 Gas Fusion Analysis
195(1)
6.14 Hall Mobility
195(1)
6.15 Mass Spectra Analysis
196(1)
6.16 Minority Carrier Diffusion Length/Lifetime/Surface Photovoltage
197(2)
6.17 Optical Methods for Impurity Evaluation
199(1)
6.18 Photoluminescence Method for Determining Impurity Concentrations
199(2)
6.19 Gamma-Ray Diffractometry
201(1)
6.20 Scanning Electron Microscopy for Defect Analysis
201(1)
6.21 Scanning Optical Microscope
202(1)
6.22 Secondary Ion Mass Spectrometer for Impurity Distribution
203(2)
6.23 Spreading Resistance and Two-Point Probe Measurement Technique
205(2)
6.24 Stress Measurements
207(2)
6.25 Transmission Electron Microscopy
209(1)
6.26 van der Pauw Resistivity Measurement Technique for Irregular-Shaped Wafers
210(1)
6.27 X-ray Technique for Crystal Perfection and Dislocation Density
210(4)
6.28 Summary
214(1)
References
214(11)
7 Resistivity and Impurity Concentration Mapping of Silicon Wafers 225(22)
7.1 Introduction
225(3)
7.2 Electrically Active and Inactive Impurities
228(1)
7.3 Surface Mapping and Concentration Contours
228(1)
7.4 Surface Roughness Mapping on a Complete Wafer
229(15)
7.5 Summary
244(1)
References
245(2)
8 Impurities in Silicon Wafers 247(46)
8.1 Effect of Intentional and Unintentional Impurities and Their Influence on Silicon Devices
247(3)
8.2 Intentional Dopant Impurities in Silicon Wafers
250(4)
8.2.1 Aluminum
250(1)
8.2.2 Antimony
250(1)
8.2.3 Arsenic
251(1)
8.2.4 Boron
252(1)
8.2.5 Gallium
253(1)
8.2.6 Phosphorus
253(1)
8.3 Unintentional Dopant Impurities in Silicon Wafers
254(28)
8.3.1 Carbon
255(4)
8.3.2 Chromium
259(1)
8.3.3 Copper
260(1)
8.3.4 Germanium
261(1)
8.3.5 Gold
261(1)
8.3.6 Helium
262(1)
8.3.7 Hydrogen
262(1)
8.3.8 Iron
263(2)
8.3.9 Nickel
265(1)
8.3.10 Nitrogen
265(3)
8.3.11 Oxygen
268(13)
8.3.12 Tin
281(1)
8.4 Other Metallic Impurities
282(1)
8.5 Summary
282(1)
References
283(10)
9 Defects in Silicon Wafers 293(54)
9.1 Introduction
293(1)
9.2 Impact of Defects in Silicon Devices and Structures
294(4)
9.3 Point Defects and Vacancies
298(6)
9.4 Line Defects
304(2)
9.5 Bulk Defects and Voids
306(4)
9.6 Dislocations and Screw Dislocations
310(2)
9.7 Swirl Defects
312(3)
9.8 Stacking Faults
315(7)
9.9 Precipitations
322(4)
9.10 Surface Pits/Crystal-Originated Particles
326(3)
9.11 Grown Vacancies and Defects
329(2)
9.12 Thermal Donors
331(1)
9.13 Slips, Cracks, and Shape Irregularities
332(2)
9.14 Stress, Bowing, and Warpage
334(3)
9.15 Summary
337(1)
References
337(10)
10 Silicon Wafer Preparation for VLSI and ULSI Processing 347(30)
10.1 Introduction
347(1)
10.2 Purity of Chemicals Used for Silicon Processing
347(1)
10.3 Degreasing of Silicon Wafers
348(1)
10.4 Removal of Metallic and Other Impurities
348(3)
10.5 Gettering of Metallic Impurities
351(11)
10.6 Denuding of Silicon Wafers
362(4)
10.7 Neutron Irradiation
366(1)
10.8 Argon Annealing of Wafers
366(2)
10.9 Hydrogen Annealing of Wafers
368(3)
10.10 Final Cleaning, Rinsing, and Wafer Drying
371(1)
10.11 Summary
371(1)
References
372(5)
11 Packing of Silicon Wafers 377(18)
11.1 Packing of Fully Processed Blank Silicon Wafers
377(11)
11.2 Storage of Wafers and Control of Particulate Contamination
388(4)
11.3 Storage of Wafers and Control of Particulate Contamination with Process-Bound Wafers
392(1)
11.4 Summary
392(1)
References
393(2)
Index 395
Golla Eranna obtained his masters degree from Sri Venkateswara University, Tirupati, India, with a top rank in the field of semiconductor physics. After that, he joined and received his Ph.D from the Indian Institute of Technology (IIT) Madras. Later, he moved to the IIT Kharagpur Microelectronics Centre. Dr. Eranna joined CEERI, Pilani, India, as a scientist and is currently a senior principal scientist. He became a professor under the Academy of Scientific and Innovative Research (CSIR, New Delhi), and regularly lectures on VLSI processing technology. He also maintains a full-fledged semiconductor device fabrication laboratory.