This microfiche constitutes the proceedings from the Custom Integrated Circuits Conference that took place in 2000. Topics covered include key methods for successful SOCs, high speed data conversion, embedded memory and architecture components and technology.
TECHNICAL SESSIONS Session 1 - Keynote Presentation Welcome and Opening Remarks Awards Presentations Keynote Speaker Introduction Brian Fitzgerald Keynote Address ``SOC: The Convergence Point for Solutions of the 21st Century 1(4) Joe Pumo Session 2 - Oversampled Analog-To-Digital Converters Timothy Rueger Douglas Garrity Introduction 142dB ΔΣ ADC with a 100nV LSB in a 3V CMOS Process 5(4) R. Naiknaware T. Fiez* A 20 Bit 25KHz Delta Sigma A/D Converter Utilizing Frequency-Shaped Chopper Stabilization Scheme 9(4) C. Wang A 1V 1mW Digital-Audio ΔΣ Modulator with 88dB Dynamic Range using Local Switch Bootstrapping 13(4) M. Dessouky A. Kaiser* An Audio ADC Delta-Sigma Modulator with 100dB SINAD and 102dB DR Using a Second-Order Mismatch-Shaping DAC 17(4) E. Fogleman J. Welz I. Galton A 12-bit 12.5 MS/s Multi-Bit ΔΣ CMOS ADC 21(6) Y. Geerts M. Steyaert W. Sansen Special Technical Session ASIC Packaging 597 Sanjay Dandia Session 3 - Advanced Communications Subsystems Jerry Molnar Kris Iniewski Introduction A 8.75-MBaud Single - Chip Digital QAM Modulator With Frequency-Agility and Beamforming Diversity 27(4) K. Cho H. Samueli* Direct Digital Frequency Synthesis Of Low-Jitter Clocks 31(4) D. Calbaza Y. Savaria A 2-V 3.7-mW Delay Locked-Loop Using Recycling Integrator Correlators for a 5-Mcps DS-CDMA Demodulator 35(4) Y. Fujimoto S. Kawama K. Lizuka M. Miyamoto D. Senderowicz* A K=3, 2Mbps Low Power Turbo Decoder for 3rd Generation W-CDMA Systems 39(4) H. Suzuki Z. Wang* K. Parhi* High-Performance Flexible All-Digital Quadrature Up and Down Converter Chip 43(6) R. Pasko L. Rijnders P. Schaumont S. Vernalde D. Durackova* Session 4 - Device And Semiconductor-Process Integration For SOC Ranbir Singh David Sunderland Introduction CMOS in the New Millennium (Invited) 49(8) T. Ning Ultra Low-Power CMOS IC Using Partially-Depleted SOI Technology 57(4) A. Ebina T. Kadowaki Y. Sato M. Yamaguchi A Fabrication Method for High Performance Embedded DRAM of 0.18μm Generation and Beyond 61(4) T. Yoshida H. Takato T. Sakurai K. Kokubun K. Hiyama A. Nomachi* Y. Takasu* M. Kishida* H. Ohtsuka* H. Naruse* Y. Morimasa* N. Yanagiya* T. Hashimoto* T. Noguchi* T. Miyamae** N. Iwabuchi*** M. Tanaka** J. Kumagai H. Ishiuchi NV-SRAM: A Nonvolatile SRAM with Back-up Ferroelectric Capacitors 65(6) T. Miwa J. Yamada H. Koike H. Toyoshima K. Amanuma S. Kobayashi T. Tatsumi Y. Maejima H. Hada T. Kunio Session 5 - Test And Reliability Mark Young Jim Gilbert Introduction A Quick And Inexpensive Method To Identify False Critical Paths Using ATPG Techniques: An Experiment With A PowerPC™ Microprocessor 71(4) J. Bhadra M. Abadir* J. Abraham Modular Test Generation and Concurrent Transparency-Based Test Translation Using Gete-Level ATPG 75(4) Y. Makris A. Orailoglu P. Vishakantaiah* Diagnosing Resistive Bridges Using Adaptive Techinques 79(4) J. Ghosh-Dastidar N. Touba A Stand-Alone Integrated Excitation/Extraction System for Analog BIST Applications 83(4) M. Hafed G. Roberts A New Design for Complete on-Chip ESD Protection 87(4) A. Wang Cell Characterization for Noise Stability 91(4) K. Shepard K. Chou* Quantitative Characterization of Substrate Noise for Physical Design Gudies in Digital Circuits 95(6) M. Nagata J. nagai T. Morie A. Iwata Session 6 - key Methods for Successful SOCs Scott Backer Jim Lipman Introduction Improving Embedded Software Design and Integration in SOCs (Invited) 101(8) G. Martin C. Lennard Coral - Automating the Design of Systems-On-Chip Using Cores 109(4) R. Bergamaschi W. Lee* D. Richardson* S. Bhattacharya M. Muhlada* R. Wagner** A. Weiner** F. White* Wire Planning for Performance and Yield Enhancement 113(4) C. Ouyang K. Ryu* H. Heineken J. Khare S. Shaikh M. dAbreu Probabilistic Aspects of Crosstalk Problems in CMOS ICs 117(4) C. Ababei R. Marculescu V. Sundarajan Applying Placement-Based Synthesis for On-Time System-on-a-Chip Design 121(4) D. Lackey Methodology for I/O Cell Placement and Checking in ASIC Designs Using Area-Array Power Grid 125(6) P. Buffet J. Natonio R. Proctor Y. Sun G. Yasar Session 7 - Innovations In Programmable Devices Steve Wilton Elliot Gould Introduction Architecture of Cluster-Based FPGAs with Memory 131(4) J. Clifford S. Wilton Cypress Delta39K - A Memory-Rich, High Performance, Scalable CPLD Architecture 135(4) A. Kennings H. Mohammed J. P. Skudlarek B. Tian* Dynamic Clock Management for Low Power Applications in FPGAs 139(4) I. Brynjolfson Z. Zilic A Million Gate PLD with 622MHz I/O Interface, Multiple PLLs and High Performance Embedded CAM 143(4) S. Cheung K. Chua B. Ang T. Chong W. Goay W. Koay S. Kuan C. Lim J. Oon T. See C. Sung K. Tan Y. Tan C. Wong Parallel and Scalable Architecture for Solving SATisfiability on Reconfigurable FPGA 147(4) T. Pagarani F. Kocan D. G. Saab J.A. Abraham* Spatial - Temporal Mapping of Real Applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI 151(4) K. Furuta T. Fujii M. Motomura K. Wakabayashi M. Yamashina Field Configurable System-on-Chip-Device Architecture 155(6) S. Knapp D. Tavana Session 8 - Low-Power Low-Voltage Wireless Systems Vincent Von Kaenel Peter Kinget Introduction CMOS RF Design - The Low Power Dimension (Invited) 161(6) Q. Huang A Low-Power CMOS Super-Regenerative Receiver at 1 GHz 167(4) A. Vouilloz C. Dehollain M. Declercq A 1v, 1mW, 434 MHz FSK Receiver Fully Integrated in a Standard Digital CMOS Process 171(4) A. Porret T. Melly D. Python C. Enz* E. Vittoz* A Dual-Band RF Front-End for WCDMA and GSM Applications 175(4) J. Ryynanen K. Kivekas J. Jussila A. Parssinen K. Halonen A 1.2 V, 433 MHz, 10dBm, 38 Global Efficiency FSK Transmitter Integrated in a Standard Digital CMOS Process 179(4) T. Melly A. Porret C. Enz* E. Vittoz* Frequency-Scalable SiGe Bipolar RFIC Front-end Design 183(6) O. Shanaa I. Linscott L. Tyler Session 9 - MOS Device Modeling Hidetoshi Onodera Steffen Rochel Introduction MOS Transitor Modeling for RF Integrated Circuit Design (Invited) 189(8) C. Enz BSIMPD: A Partial-Depletion SOI MOSFET Model for Deep-Submicron CMOS Designs 197(4) P. Su S. Fung* S. Tang F. Assaderaghi* C. Hu New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation 201(4) Y.Cao T. Sato* M. Orshansky D. Sylvester** C. Hu RFCMOS Extension Model Accurate up to 40 GHz with Distributed Junction Diode 205(4) T. Kuo Advanced Compact Model for Short-Channel MOS Transistors 209(4) O. da Costa Gouveia-Filho* A. Cunha** M. Schneider C. Galup-Montoro S-TFT: An Analytical Model of Polysilicon Thin-Film Transistors for Circuit Simulation 213(6) G.-Y. Yang Y.-G. Kim T.-S. Kim J.-T. Kong Session 10 - System-On-A-Chip: From Concept To Consumer Michele Taliercio Ann Rincon Introduction A 64-min Single-Chip Voice Recorder/Player using Embedded 4bit/cell Flash Memory 219(4) M. Borgatti A. Rocchi M. Bisio M. Besana L. Navoni P. Rolandi A Low-Power System-on-Chip for the Documentation of Road Accidents 223(4) L. Bolcioni R. Guerrieri Designing High-Speed Serial Ports Using Standard ASIC Library Elements, Tools and Design Methodologies 227(4) P. Freud A 9-M Tr. Access Network System-On-a-Chip for Mega-bit Internet Access at Home 231(4) S. Kozu T. Aramaki C. Ikeda Y. Kuroda S. Kawanago M. Okada H. Kariya M. Manabe H. Utani E. Sudou Y. Oda H. Suzuki A 300K-gate 0.5μm CMOS Implementation of An 8-VSB Receiver IC 235(4) I. Lee D. Kim S. Lee K. Kwon J. Kim I. Kim Y. Kim S. Park C. Kim H. Jung G. Chang Secure Contactless Smartcard ASIC with DPA Protection 239(6) P. Rakers L. Connell T. Collins* D. Russell* Session 11 - High Speed Data Conversion L. Richard Carley Yusuf Haque Introduction A Broadband 10 GHz Track-and-Hold in Si/SiGe HBT Technology 245(4) J. Jensen L. Larson A 6-bit 1 GHz Acquisition Speed CMOS Flash ADC with Digital Error Correction 249(4) K. Uyttenhove A. Marques* M. Steyaert A 100-MSPS 8-b CMOS Subranging ADC with Parametric Operation From 3.8 V Down to 2.2 V 253(4) R. Taft M. Tursi A 10-bit, 3V, 100MS/s Pipelined ADC 257(4) D. Nairn A Highly Linear Low-Power 10 bit DAC for GSM 261(4) P. Ferguson X. Haurie G. Temes* A 10 bit 1-G Sample/s Nyquist Current-Steering CMOS D/A Converter 265(6) A. Van den Bosch M. Borremans M. Steyaert W. Sansen Session 12 - Embedded Memory Cormac OConnell Joe Ting Introduction Design Methodology of the Embedded DRAM with the Virtual Socket Architecture 271(4) M. Kinoshita T. Yamauchi T. Amano K. Dosaka K. Arimoto Low-Power Technique for On-Chip Memory Using Biased Partitioning and Access Concentration 275(4) N. Kawabe K. Usami A 1.8-V Embedded 18-Mb DRAM Macro with a 9-ns RAS Access Time and Memory Cell Efficiency of 33 279(4) Y. Yokoyama N. Itoh M. Katayama* K. Takashima H. Akasaki* M. Kaneda* T. Ueda* Y. Tanaka E. Yamasaki* M. Todokoro* K. Toriyama H. Miki** M. Yagyu** T. Kobayashi S. Miyaoka N. Tamba An Ultra-High-Density High-Speed Loadless Four-Transistor SRAM Macro with a Dual-Layered Twisted Bit-Line and a Triple-Well Shield 283(4) K. Noda K. Matsui S. Ito S. Masuoka H. Kawamoto N. Ikezawa K. Takeda* Y. Aimoto* N. Nakamura* H. Toyoshima* T. Iwasaki** T. Horiuchi SRAM Embedded Memory with Low Cost, FLASH Eeprom-Switch-Controlled Redundancy 287(4) R. McPartland D. Loeper F. Higgins* R. Singh** G. MacDonald G. Komoriya S. Aymeloglu M. DePaolis C. Leung** Embedded DRAM: An Element and Circuit Evaluation 291(4) P. Diodato J. ONeill* Y.-H. Wong G. Alers H. Vaidya** S. Chaudhry*** W. Lindenberger A. Dumbri+ C.-T. Liu W. Lai Design Validation of .18 μm 1 GHz Cache and Register Arrays 295(8) D. Malone P. Bunce J. DellaPietro J. Davis J. Dawson T. Knips D. Plass P. Pritzlaff K. Reyer Session 13 - Afternoon Panel Discussion Timing Closure - Can Synthesis and Physical Design Really Get Along? 299(4) Session 14 - High-Speed Data Communication/Storage Circuits Sang-Soo Lee Fang Lu Introduction A CMOS ADSL Codec for Central Office Applications 303(4) P. Siniscalchi J. Pitz R. Hester S. DeSoto M. Wang S. Sridharan R. Halbach D. Richardson W. Bright M. Saraj J. Hellums C. Betty G. Westphal A 4 Channel Analog Front End for Central Office ADSL Modems 307(4) J. Kenney F. Sabouri V. Leung J. Guido E. Zimany A. Agrillo J. Trackim J. Khoury* R. Shariatdoust A Single-Chip Universal Burst Receiver for Cable Modem/Digital Cable-TV Applications 311(4) F. Lu J. Min S. Liu K. Cameron C. Jones O. Lee J. Li A. Buchwald S. Jantzi C. Ward K. Choi J. Searle H. Samueli A Single Chip 155Mbps/140Mbps SDH/PDH Transceiver 315(4) J. Guinea L. Tomasini S. Maggio* M. Rutar* A 450Mbit/s Parallel Read/Write Channel with Parity Check and 16-State Time Variant Viterbi 319(4) G. Bollati A. Dati G. Betti I. Bietti F. Brianti M. Bruccoleri M. Coltella P. Demartini M. Demicheli P. Gadducci S. Marchese D. Ottini V. Pisati F. Rezzi A. Rossi P. Savo C. Tonci R. Castello* A Versatile Low-Power Power Line FSK Transceiver 323(4) R. Cappelletti A. Baschirotto* An Analog Front-End LSI with On-Chip Isolator for V.90 56kbps Modems 327(6) N. Kanekawa Y. Kojima S. Yokutake M. Nemoto T. Iwasaki K. Takami Y. Takeuchi* A. Yano* Y. Shima* Session 15 - Radio Integration: Architecture, Components and Technology Trudy Stetzler Georges Gielen Introduction Silicon Radio Integration: Architectures and Technology: From Cartesian Zero IF Receive & Transmit to Polar Zero I and Q, From Silicon Bipolar to Bulk and SOI CMOS (Invited) 333(8) J. Sevenhans A 900-MHz T/R Switch with a 0.8-dB Insertion Loss Implemented in a 0.5-μm CMOS Process 341(4) F. Huang K. O Stacked Inductors and 1-to-2 Transformers in CMOS Technology 345(4) A. Zolfaghari A. Chan B. Razavi An Integrated Capacitively Coupled Transformer and Its Application for RF ICs 349(4) L.-P. Wong C. Snyder T. Manku S. Kovacic* Measuring and Modeling the Effects of Substrate Noise on the LNA for a CMOS GPS Receiver 353(4) M. Xu D. Su D. Shaeffer T. Lee B. Wooley Active Substrate Noise Suppression In Mixed-Signal Circuits Using On-Chip Driven Guard Rings 357(4) W. Winkler F. Herzel Impact of Technology Scaling on CMOS RF Devices and Circuits 361(10) E. Abou-Allam T. Manku M. Ting M. Obrecht Session 16 - Evening Panel Discussion SOC: Does it make Dollars and Sense? 365(2) Session 17 - Evening Panel Discussion Outsourcing Design: Blessing or Curse? 367(4) Session 18 - Analog Techniques Jose Cruz Venugopal Gopinathan Introduction CMOS DLL Based 2V, 3.2ps Jitter, 1GHz Clock Synthesizer and Temperature Compensated Tunable Oscillator 371(4) D. Foley M. Flynn* A 900MHz, 2.5mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop 375(4) T.-H. Lin W. Kaiser A 2.5-Gb/s Clock Recovery Circuit for NRZ Data in 0.4-μm CMOS Technology 379(4) S. Anand B. Razavi A 65 mW, 0.4-2.3 GHz Bandpass Filter for Satellite Receivers 383(4) J. van der Tang D. Kasperkovitz A. Bretveld* A 3V Linear Input Range Tunable CMOS Transconductor and Its Application to a 3.3V 1.1MHz Chebyshev Low-Pass Gm-C Filter for ADSL 387(4) J.-Y. Lee C.-C. Tu W.-H. Chen A CMOS gm-C IF Filter for Bluetooth 391(4) P. Andreani S. Mattisson* A CMOS Readout Circuit for Pico-Ampere Thin Film Pyroelectric Array Detectors 395(6) T. Reimann F. Krummenacher B. Willing P. Muralt M. Declercq Session 19 - Low Power And Dynamic Design Techniques Ken Au Michio Yotsuyanagi Introduction Effect of Technology Scaling on Digital CMOS Logic Styles (Invited) 401(8) M. Allam M. Anis M. Elmasry Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration 409(4) T. Inukai M. Takamiya K. Nose H. Kawaguchi T. Hiramoto T. Sakurai Power Minimization by Simultaneous Dual-Vth Assignment and Gate-sizing 413(4) L. Wei K. Roy C.-K. Koh 5.5V Tolerant I/O in a 2.5V 0.25μm CMOS Technology 417(4) A.-J. Annema G. Geelen* P. de Jong** Dynamic Current Mode Logic (DyCML), A New Low-Power High-Performance Logic Family 421(4) M. Allam M. Elmasry A Noise-Tolerant Dynamic Circuit Design Technique 425(6) G. Balamurugan N. Shanbhag Session 20 - Noise Analysis And Circuit Modeling For RF Applications Georges Gielen Edoardo Charbon Introduction Noise in Mixers, Oscillators, Samplers, and Logic: An Introduction to Cyclostationary Noise (Invited) 431(8) J. Phillips K. Kundert Complete Noise Analysis for CMOS Switching Mixers Via Stochastic Differential Equations 439(4) D. Ham A. Hajimiri Analysis of Jitter due to Power-Supply Noise in Phase-Locked Loops 443(4) P. Heydari M. Pedram Nonlinear Behavioral Modeling and Simulation of Phase-Locked and Delay-Locked Systems 447(4) L. Wu H. Jin W. Black Automated Extraction of Nonlinear Circuit Macromodels 451(4) J. Phillips Finite-Length Signal Quantization using Discrete Optimization 455(6) M. Chapman* A. Demir P. Feldmann Session 21 - Digital And Hybrid Signal Processing Alan Willson Jackie Snyder Introduction A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire 461(4) T.-C. Lee B. Razavi A Low Complexity Joint Equalizer and Decoder for 1000Base-T Gigabit Ethernet 465(4) E. Haratsch K. Azadet A PN-Acquisition ASIC for Wireless CDMA Systems 469(4) C. Deng C. Chien* Media Processor Core Architecture for Realtime, Bi-Directional MPEG4/H.26X Codec with 30 fr/s for CIF-Video 473(4) T. Kamemaru H. Ohira H. Suzuki K. Asano M. Yoshimoto T. Murakami Efficient and Reusable Time-Sharing Architectures for Equalizer Structures 477(4) S. Meier M. Schobinger A Locally-Clocked Dynamic Logic Serial/Parallel Multiplier 481(6) G. Hoyer C. Sechen Session 22 - CAD Methods For Deep Sub-Micron Designs N.S. Nagaraj Peter Feldmann Introduction On-Chip Inductance Modeling and RLC Extraction of VLSI Interconnects for Circuit 487(4) X. Qi G. Wang Z. Yu R. Dutton T. Young* N. Chang** Parasitic Extraction for Multimillion-Transistor Integrated Circuits: Methodology and Design Experiences 491(4) E. You S. Choe C. Kim L. Varadadesikan K. Aingaran J. MacDonald* Multi-Aggressor Relative Window Method for Timing Analysis Including Crosstalk Delay Degradation 495(4) Y. Sasaki K. Yano Multi-Dimensional Model Reduction of VLSI Interconnects 499(4) P. Gunupudi M. Nakhla A Novel High-Performance Predictable Circuit Architecture for the Deep Sub-micron Era 503(4) Y. Im K. Roy Low Power Bus Coding Techniques Considering Inter-wire Capacitances 507(4) P. Sotiriadis A. Chandrakasan WiCkeD: Analog Circuit Synthesis Incorporating Mismatch 511(6) K. Antreich J. Eckmueller* H. Graeb M. Pronath F. Schenkel R. Schwencker* S. Zizala* Session 23 - IP Development And Protection Alex Kurosawa Terry Sideris Introduction On Intellectual Property Protection (Invited) 517(8) E. Charbon I. Torunoglu An Analysis of the Design Processes Required for the Technology Conversion of SoC Intellectual Property 525(4) J. Nash P. Smith Firm IP Development: Methodology and Deliverables 529(4) A. Ranjit P. Ramkumar V. Noel A New Paradigm for Very Flexible SONET/SDH IP-Modules 533(4) T. Rower M. Stadler M. Thalmann* H. Kaeslin N. Felber W. Fichtner Merging Hardware and Software: Intellectual Property Cores for Internet Applications 537(6) G. Bollano S. Claretto E. Filippi A. Torielli M. Turolla Session 24 - Audio And Visual Signal Processing Dawn Fitzgerald Alan Willson Introduction VLSI Implementatation of a Realtime Wavelet Video Coder 543(4) R. Omaki Y. Dong M. Miki M. Furuie S. Yamada D. Taki M. Tarui G. Fujita T. Onoye* I. Shirakawa A Partitioned Wavelet-based Approach for Image Compression using FPGAs 547(4) J. Ritter Paul Molitor Flova: A Four-issue VLIW Geometry Processor with SIMD Instructions and Lighting Acceleration Unit 551(4) S.-J. Nam B.-W. Kim Y.-H. Im Y.-S. Kwon J.-H. Lee Y.-W. Cheon S.-J. Byun D.-H. Lee C.-M. Kyung Novel VLIW Code Compaction Method for a 3D Geometry Processor 555(4) H. Suzuki H. Makino Y. Matsuda Multi-Thread VLIW Processor Architecture For HDTV Decoding 559(4) H. Kim W.-S. Yang M.-C. Shin S.-J. Min* S.-O. Bae* I.-C. Park A Full Accuracy MPEG1 Audio Layer 3 (MP3) Decoder with Internal Data Converters 563(6) S. Hong B. Park Y. Song H. Seo J. Kim H. Lee D. Kim M. Song* Session 25 - Oscillators, PLLs And Applications Peter Kinget Vincent VonKaenel Introduction Physical Processes of Phase Noise in Differential LC Oscillators 569(4) J. Rael A. Abidi A New Approach to Fully Intregrated CMOS LC-Oscillators with a Very Large Tuning Range 573(4) F. Herzel H. Erzgraber N. Ilkov A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz Fully Tuneable LC CMOS VCO 577(4) F. Svelto S. Deantoni* R. Castello** A 10 GHz CMOS Distributed Voltage Controlled Oscillator 581(4) H. Wu A. Hajimiri A 1.8 GHz Highly-Tunable Low-Phase-Noise CMOS VCO 585(4) B. De Muer N. Itoh* M. Borremans M. Steyaert A Fully-Intergrated Low Phase-Noise Nested-Loop PLL for Frequency Synthesis 589(4) A. Hafez M. Elmasry A Low Power High Spectral Purity Frequency Translational Loop for Wireless Applications 593 M. Margarit M. Deen*
