A September 2007 symposium gathered academics, research scientists, and industrial practitioners in the global defect and fault tolerance (DFT) community to examine traditional DFT topics, such as error correction and fault tolerant designs, as well as new topics, including DFT in networks-on-chips, nanotechnology, and soft errors. This proceedings presents 45 regular papers from the symposium and 12 papers from a special poster session. Papers are organized in sections on reliable NoCs and SoCs, single event effects, defect and fault tolerance, fault injection and reliability analysis, testing and design for testability, defect and fault tolerance, dependable solutions for memories and storage, reliable design techniques, emerging technologies, and reliable applications. Papers from the poster session explore realms such as timing-aware diagnosis for small delay defects, testing of asynchronous NULL conventional logic circuits in synchronous-based designs, and production yield and self-configuration in massively defective nanochips. There is no subject index. Annotation ©2007 Book News, Inc., Portland, OR (booknews.com)
