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Design of Analog CMOS Integrated Circuits 2nd edition [Kõva köide]

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  • Formaat: Hardback, 800 pages, kõrgus x laius x paksus: 262x213x33 mm, kaal: 1633 g, 1136 Illustrations
  • Ilmumisaeg: 16-Feb-2016
  • Kirjastus: McGraw-Hill Inc.,US
  • ISBN-10: 0072524936
  • ISBN-13: 9780072524932
Teised raamatud teemal:
Design of Analog CMOS Integrated Circuits 2nd editionSuurem pilt
  • Formaat: Hardback, 800 pages, kõrgus x laius x paksus: 262x213x33 mm, kaal: 1633 g, 1136 Illustrations
  • Ilmumisaeg: 16-Feb-2016
  • Kirjastus: McGraw-Hill Inc.,US
  • ISBN-10: 0072524936
  • ISBN-13: 9780072524932
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780072524932.html
Märksõnad:

The second edition of Design of Analog CMOS Integrated Circuits by Behzad Razavi, deals with the analysis and design of analog CMOS integrated circuits, emphasizing fundamentals as well as new paradigms that students and practicing engineers need to master in today's industry. Since analog design requires both intuition and rigor, each concept is first introduced from an intuitive perspective and subsequently treated by careful analysis. The objective is to develop both a solid foundation and methods of analyzing circuits by inspection so that the reader learns what approximations can be made in which circuits and how much error to expect in each approximation. This approach also enables the reader to apply the concepts to bipolar circuits with little additional effort.

Preface to the Second Edition iv
About the Author ix
1 Introduction to Analog Design 1(6)
1.1 Why Analog?
1(3)
1.1.1 Sensing and Processing Signals
1(1)
1.1.2 When Digital Signals Become Analog
2(1)
1.1.3 Analog Design Is in Great Demand
3(1)
1.1.4 Analog Design Challenges
4(1)
1.2 Why Integrated?
4(1)
1.3 Why CMOS"
5(1)
1.4 Why This Book?
5(1)
1.5 Levels of Abstraction
5(2)
2 Basic MOS Device Physics 7(38)
2.1 General Considerations
7(3)
2.1.1 MOSFET as a Switch
7(1)
2.1.2 MOSFET Structure
8(1)
2.1.3 MOS Symbols
9(1)
2.2 MOS UV Characteristics
10(10)
2.2.1 Threshold Voltage
10(2)
2.2.2 Derivation of UV Characteristics
12(7)
2.2.3 MOS Transconductance
19(1)
2.3 Second-Order Effects
20(6)
2.4 MOS Device Models
26(10)
2.4.1 MOS Device Layout
26(1)
2.4.2 MOS Device Capacitances
27(4)
2.4.3 MOS Small-Signal Model
31(3)
2.4.4 MOS SPICE models
34(1)
2.4.5 NMOS Versus PMOS Devices
35(1)
2.4.6 Long-Channel Versus Short-Channel Devices
35(1)
2.5 Appendix A: FinFETs
36(1)
2.6 Appendix B: Behavior of a MOS Device as a Capacitor
37(8)
3 Single-Stage Amplifiers 45(55)
3.1 Applications
45(1)
3.2 General Considerations
45(2)
3.3 Common-Source Stage
47(21)
3.3.1 Common-Source Stage with Resistive Load
47(5)
3.3.2 CS Stage with Diode-Connected Load
52(6)
3.3.3 CS Stage with Current-Source Load
58(1)
3.3.4 CS Stage with Active Load
59(1)
3.3.5 CS Stage with Triode Load
60(1)
3.3.6 CS Stage with Source Degeneration
61(7)
3.4 Source Follower
68(7)
3.5 Common-Gate Stage
75(7)
3.6 Cascode Stage
82(10)
3.6.1 Folded Cascode
90(2)
3.7 Choice of Device Models
92(8)
4 Differential Amplifiers 100(34)
4.1 Single-Ended and Differential Operation
100(3)
4.2 Basic Differential Pair
103(15)
4.2.1 Qualitative Analysis
104(2)
4.2.2 Quantitative Analysis
106(10)
4.2.3 Degenerated Differential Pair
116(2)
4.3 Common-Mode Response
118(5)
4.4 Differential Pair with MOS Loads
123(3)
4.5 Gilbert Cell
126(8)
5 Current Mirrors and Biasing Techniques 134(39)
5.1 Basic Current Mirrors
134(5)
5.2 Cascode Current Mirrors
139(7)
5.3 Active Current Mirrors
146(14)
5.3.1 Large-Signal Analysis
149(3)
5.3.2 Small-Signal Analysis
152(4)
5.3.3 Common-Mode Properties
156(3)
5.3.4 Other Properties of Five-Transistor OTA
159(1)
5.4 Biasing Techniques
160(13)
5.4.1 CS Biasing
161(3)
5.4.2 CG Biasing
164(1)
5.4.3 Source Follower Biasing
165(1)
5.4.4 Differential Pair Biasing
166(7)
6 Frequency Response of Amplifiers 173(46)
6.1 General Considerations
173(7)
6.1.1 Miller Effect
174(5)
6.1.2 Association of Poles with Nodes
179(1)
6.2 Common-Source Stage
180(8)
6.3 Source Followers
188(5)
6.4 Common-Gate Stage
193(3)
6.5 Cascode Stage
196(2)
6.6 Differential Pair
198(5)
6.6.1 Differential Pair with Passive Loads
198(3)
6.6.2 Differential Pair with Active Load
201(2)
6.7 Gain-Bandwidth Trade-Offs
203(3)
6.7.1 One-Pole Circuits
204(1)
6.7.2 Multi-Pole Circuits
205(1)
6.8 Appendix A: Extra Element Theorem
206(2)
6.9 Appendix B: Zero-Value Time Constant Method
208(4)
6.10 Appendix C: Dual of Miller's Theorem
212(7)
7 Noise 219(55)
7.1 Statistical Characteristics of Noise
219(9)
7.1.1 Noise Spectrum
221(3)
7.1.2 Amplitude Distribution
224(1)
7.1.3 Correlated and Uncorrelated Sources
225(1)
7.1.4 Signal-to-Noise Ratio
226(1)
7.1.5 Noise Analysis Procedure
227(1)
7.2 Types of Noise
228(8)
7.2.1 Thermal Noise
228(6)
7.2.2 Flicker Noise
234(2)
7.3 Representation of Noise in Circuits
236(7)
7.4 Noise in Single-Stage Amplifiers
243(11)
7.4.1 Common-Source Stage
244(5)
7.4.2 Common-Gate Stage
249(4)
7.4.3 Source Followers
253(1)
7.4.4 Cascode Stage
254(1)
7.5 Noise in Current Mirrors
254(2)
7.6 Noise in Differential Pairs
256(7)
7.7 Noise-Power Trade-Off
263(1)
7.8 Noise Bandwidth
264(1)
7.9 Problem of Input Noise Integration
265(1)
7.10 Appendix A: Problem of Noise Correlation
265(9)
8 Feedback 274(70)
8.1 General Considerations
274(12)
8.1.1 Properties of Feedback Circuits
275(7)
8.1.2 Types of Amplifiers
282(2)
8.1.3 Sense and Return Mechanisms
284(2)
8.2 Feedback Topologies
286(12)
8.2.1 Voltage-Voltage Feedback
286(5)
8.2.2 Current-Voltage Feedback
291(3)
8.2.3 Voltage-Current Feedback
294(3)
8.2.4 Current-Current Feedback
297(1)
8.3 Effect of Feedback on Noise
298(1)
8.4 Feedback Analysis Difficulties
299(4)
8.5 Effect of Loading
303(12)
8.5.1 Two-Port Network Models
303(1)
8.5.2 Loading in Voltage-Voltage Feedback
304(4)
8.5.3 Loading in Current-Voltage Feedback
308(2)
8.5.4 Loading in Voltage-Current Feedback
310(3)
8.5.5 Loading in Current-Current Feedback
313(2)
8.5.6 Summary of Loading Effects
315(1)
8.6 Bode's Analysis of Feedback Circuits
315(16)
8.6.1 Observations
315(2)
8.6.2 Interpretation of Coefficients
317(3)
8.6.3 Bode's Analysis
320(5)
8.6.4 Blackman's Impedance Theorem
325(6)
8.7 Middlebrook's Method
331(1)
8.8 Loop Gain Calculation Issues
332(4)
8.8.1 Preliminary Concepts
332(2)
8.8.2 Difficulties with Return Ratio
334(2)
8.9 Alternative Interpretations of Bode's Method
336(8)
9 Operational Amplifiers 344(66)
9.1 General Considerations
344(5)
9.1.1 Performance Parameters
344(5)
9.2 One-Stage Op Amps
349(12)
9.2.1 Basic Topologies
349(4)
9.2.2 Design Procedure
353(1)
9.2.3 Linear Scaling
354(1)
9.2.4 Folded-Cascode Op Amps
355(3)
9.2.5 Folded-Cascode Properties
358(1)
9.2.6 Design Procedure
359(2)
9.3 Two-Stage Op Amps
361(3)
9.3.1 Design Procedure
363(1)
9.4 Gain Boosting
364(9)
9.4.1 Basic Idea
364(4)
9.4.2 Circuit Implementation
368(3)
9.4.3 Frequency Response
371(2)
9.5 Comparison
373(1)
9.6 Output Swing Calculations
373(1)
9.7 Common-Mode Feedback
374(14)
9.7.1 Basic Concepts
374(3)
9.7.2 CM Sensing Techniques
377(3)
9.7.3 CM Feedback Techniques
380(6)
9.7.4 CMFB in Two-Stage Op Amps
386(2)
9.8 Input Range Limitations
388(2)
9.9 Slew Rate
390(7)
9.10 High-Slew-Rate Op Amps
397(3)
9.10.1 One-Stage Op Amps
397(2)
9.10.2 Two-Stage Op Amps
399(1)
9.11 Power Supply Rejection
400(2)
9.12 Noise in Op Amps
402(8)
10 Stability and Frequency Compensation 410(49)
10.1 General Considerations
410(4)
10.2 Multipole Systems
414(2)
10.3 Phase Margin
416(4)
10.4 Basic Frequency Compensation
420(6)
10.5 Compensation of Two-Stage Op Amps
426(7)
10.6 Stewing in Two-Stage Op Amps
433(3)
10.7 Other Compensation Techniques
436(3)
10.8 Nyquist's Stability Criterion
439(20)
10.8.1 Motivation
439(1)
10.8.2 Basic Concepts
440(2)
10.8.3 Construction of Polar Plots
442(5)
10.8.4 Cauchy's Principle
447(1)
10.8.5 Nyquist's Method
447(3)
10.8.6 Systems with Poles at Origin
450(4)
10.8.7 Systems with Multiple 180° Crossings
454(5)
11 Nanometer Design Studies 459(50)
11.1 Transistor Design Considerations
459(1)
11.2 Deep-Submicron Effects
460(3)
11.3 Transconductance Scaling
463(3)
11.4 Transistor Design
466(6)
11.4.1 Design for Given ID and Vps,min
466(3)
11.4.2 Design for Given gm and ID
469(1)
11.4.3 Design for Given gm and Vps,min
470(1)
11.4.4 Design for a Given gm
471(1)
11.4.5 Choice of Channel Length
472(1)
11.5 Op Amp Design Examples
472(23)
11.5.1 Telescopic Op Amp
473(14)
11.5.2 Two-Stage Op Amp
487(8)
11.6 High-Speed Amplifier
495(12)
11.6.1 General Considerations
496(4)
11.6.2 Op Amp Design
500(1)
11.6.3 Closed-Loop Small-Signal Performance
501(1)
11.6.4 Op Amp Scaling
502(3)
11.6.5 Large-Signal Behavior
505(2)
11.7 Summary
507(2)
12 Bandgap References 509(30)
12.1 General Considerations
509(1)
12.2 Supply-Independent Biasing
509(4)
12.3 Temperature-Independent References
513(10)
12.3.1 Negative-TC Voltage
513(1)
12.3.2 Positive-TC Voltage
514(1)
12.3.3 Bandgap Reference
515(8)
12.4 PTAT Current Generation
523(1)
12.5 Constant-Gm Biasing
524(1)
12.6 Speed and Noise Issues
525(4)
12.7 Low-Voltage Bandgap References
529(4)
12.8 Case Study
533(6)
13 Introduction to Switched-Capacitor Circuits 539(37)
13.1 General Considerations
539(4)
13.2 Sampling Switches
543(12)
13.2.1 MOSFETS as Switches
543(4)
13.2.2 Speed Considerations
547(2)
13.2.3 Precision Considerations
549(4)
13.2.4 Charge Injection Cancellation
553(2)
13.3 Switched-Capacitor Amplifiers
555(13)
13.3.1 Unity-Gain Sampler/Buffer
555(7)
13.3.2 Noninverting Amplifier
562(5)
13.3.3 Precision Multiply-by-Two Circuit
567(1)
13.4 Switched-Capacitor Integrator
568(3)
13.5 Switched-Capacitor Common-Mode Feedback
571(5)
14 Nonlinearity and Mismatch 576(31)
14.1 Nonlinearity
576(15)
14.1.1 General Considerations
576(3)
14.1.2 Nonlinearity of Differential Circuits
579(2)
14.1.3 Effect of Negative Feedback on Nonlinearity
581(2)
14.1.4 Capacitor Nonlinearity
583(1)
14.1.5 Nonlinearity in Sampling Circuits
584(1)
14.1.6 Linearization Techniques
585(6)
14.2 Mismatch
591(16)
14.2.1 Effect of Mismatch
593(5)
14.2.2 Offset Cancellation Techniques
598(4)
14.2.3 Reduction of Noise by Offset Cancellation
602(1)
14.2.4 Alternative Definition of CMRR
603(4)
15 Oscillators 607(44)
15.1 General Considerations
607(2)
15.2 Ring Oscillators
609(9)
15.3 LC Oscillators
618(12)
15.3.1 Basic Concepts
618(3)
15.3.2 Cross-Coupled Oscillator
621(3)
15.3.3 Colpitts Oscillator
624(2)
15.3.4 One-Port Oscillators
626(4)
15.4 Voltage-Controlled Oscillators
630(14)
15.4.1 Tuning in Ring Oscillators
633(8)
15.4.2 Tuning in LC Oscillators
641(3)
15.5 Mathematical Model of VCOs
644(7)
16 Phase-Locked Loops 651(40)
16.1 Simple PLL
651(15)
16.1.1 Phase Detector
651(2)
16.1.2 Basic PLL Topology
653(7)
16.1.3 Dynamics of Simple PLL
660(6)
16.2 Charge-Pump PLLs
666(11)
16.2.1 Problem of Lock Acquisition
666(1)
16.2.2 Phase/Frequency Detector
667(2)
16.2.3 Charge Pump
669(2)
16.2.4 Basic Charge-Pump PLL
671(6)
16.3 Nonideal Effects in PLLs
677(6)
16.3.1 PFD/CP Nonidealities
677(4)
16.3.2 Jitter in PLLs
681(2)
16.4 Delay-Locked Loops
683(2)
16.5 Applications
685(6)
16.5.1 Frequency Multiplication and Synthesis
685(2)
16.5.2 Skew Reduction
687(1)
16.5.3 Jitter Reduction
688(3)
17 Short-Channel Effects and Device Models 691(21)
17.1 Scaling Theory
691(4)
17.2 Short-Channel Effects
695(6)
17.2.1 Threshold Voltage Variation
695(2)
17.2.2 Mobility Degradation with Vertical Field
697(1)
17.2.3 Velocity Saturation
698(2)
17.2.4 Hot Carrier Effects
700(1)
17.2.5 Output Impedance Variation with Drain-Source Voltage
700(1)
17.3 MOS Device Models
701(7)
17.3.1 Level 1 Model
702(1)
17.3.2 Level 2 Model
702(2)
17.3.3 Level 3 Model
704(2)
17.3.4 BSIM Series
706(1)
17.3.5 Other Models
707(1)
17.3.6 Charge and Capacitance Modeling
707(1)
17.3.7 Temperature Dependence
708(1)
17.4 Process Corners
708(4)
18 CMOS Processing Technology 712(21)
18.1 General Considerations
712(1)
18.2 Wafer Processing
713(1)
18.3 Photolithography
714(1)
18.4 Oxidation
715(1)
18.5 Ion Implantation
716(2)
18.6 Deposition and Etching
718(1)
18.7 Device Fabrication
718(12)
18.7.1 Active Devices
718(3)
18.7.2 Passive Devices
721(6)
18.7.3 Interconnects
727(3)
18.8 Latch-Up
730(3)
19 Layout and Packaging 733(41)
19.1 General Layout Considerations
733(3)
19.1.1 Design Rules
734(2)
19.1.2 Antenna Effect
736(1)
19.2 Analog Layout Techniques
736(24)
19.2.1 Multifinger Transistors
737(2)
19.2.2 Symmetry
739(4)
19.2.3 Shallow Trench Isolation Issues
743(1)
19.2.4 Well Proximity Effects
744(1)
19.2.5 Reference Distribution
744(2)
19.2.6 Passive Devices
746(7)
19.2.7 Interconnects
753(4)
19.2.8 Pads and ESD Protection
757(3)
19.3 Substrate Coupling
760(4)
19.4 Packaging
764(10)
Index 774
Behzad Razavi received the BSEE Degree from Sharif University of Technology in 1985 and the MSEE and PhDEE Degrees from Stanford University in 1988 and 1992, respectively. He was with AT&T Bell Laboratories and Hewlett-Packard Laboratories until 1996. Since 1996, he has been Associate Professor and subsequently Professor of Electrical Engineering at University of California, Los Angeles. His current research includes wireless transceivers, frequency synthesizers, phase-locking and clock recovery for high-speed data communications. and data converters.