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Design, Analysis and Test of Logic Circuits Under Uncertainty 2013 ed. [Pehme köide]

  • Formaat: Paperback / softback, 124 pages, kõrgus x laius: 235x155 mm, kaal: 2175 g, XII, 124 p., 1 Paperback / softback
  • Sari: Lecture Notes in Electrical Engineering 115
  • Ilmumisaeg: 15-Oct-2014
  • Kirjastus: Springer
  • ISBN-10: 9400797982
  • ISBN-13: 9789400797987
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  • Formaat: Paperback / softback, 124 pages, kõrgus x laius: 235x155 mm, kaal: 2175 g, XII, 124 p., 1 Paperback / softback
  • Sari: Lecture Notes in Electrical Engineering 115
  • Ilmumisaeg: 15-Oct-2014
  • Kirjastus: Springer
  • ISBN-10: 9400797982
  • ISBN-13: 9789400797987
Combining theory with practical examples, this volume presents a comprehensive overview of logic circuits. The text presents techniques used to analyze, design and test logic circuits with probabilistic behavior, and provides a multidisciplinary approach to uncertainty.

Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.
1 Introduction
1(20)
1.1 Background and Motivation
2(5)
1.1.1 Soft Errors
2(2)
1.1.2 Trends in CMOS
4(1)
1.1.3 Technologies Beyond CMOS
5(2)
1.2 Related Work
7(9)
1.2.1 Probabilistic Analysis of Circuits
7(1)
1.2.2 Soft-Error Rate Analysis
8(3)
1.2.3 Fault-Tolerant Design
11(4)
1.2.4 Soft-Error Testing
15(1)
1.3 Organization
16(5)
References
17(4)
2 Probabilistic Transfer Matrices
21(16)
2.1 PTM Algebra
22(8)
2.1.1 Basic Operations
23(3)
2.1.2 Additional Operation
26(3)
2.1.3 Handling Correlations
29(1)
2.2 Applications
30(7)
2.2.1 Fault Modeling
31(1)
2.2.2 Modeling Glitch Attenuation
31(4)
2.2.3 Error Transfer Functions
35(1)
References
36(1)
3 Computing with Probabilistic Transfer Matrices
37(16)
3.1 Compressing Matrices with Decision Diagrams
37(8)
3.1.1 Computing Circuit PTMs
41(4)
3.2 Improving Scalability
45(8)
3.2.1 Dynamic Ordering of Evaluation
45(2)
3.2.2 Hierarchical Reliability Estimation
47(4)
3.2.3 Approximation by Sampling
51(1)
References
52(1)
4 Testing Logic Circuits for Probabilistic Faults
53(10)
4.1 Test-Vector Sensitivity
54(3)
4.2 Test Generation
57(6)
References
61(2)
5 Signature-Based Reliability Analysis
63(30)
5.1 SER in Combinational Logic
64(7)
5.1.1 Fault Models for Soft Errors
64(1)
5.1.2 Signatures and Observability Don't-Cares
65(3)
5.1.3 SER Evaluation
68(2)
5.1.4 Multiple-Fault Analysis
70(1)
5.2 SER Analysis in Sequential Logic
71(5)
5.2.1 Steady-State and Reachability Analysis
73(1)
5.2.2 Error Persistence and Sequential Observability
74(2)
5.3 Additional Masking Mechanisms
76(9)
5.3.1 Incorporating Timing Masking into SER Estimation
76(4)
5.3.2 Electrical Attenuation
80(4)
5.3.3 An Overall SER Evaluation Framework
84(1)
5.4 Empirical Validation
85(8)
References
90(3)
6 Design for Robustness
93(22)
6.1 Improving the Reliability of Combinational Logic
93(6)
6.1.1 Signature-Based Design
94(2)
6.1.2 Impact Analysis and Gate Selection
96(1)
6.1.3 Local Logic Rewriting
97(1)
6.1.4 Gate Relocation
98(1)
6.2 Improving Sequential Circuit Reliability and Testability
99(5)
6.2.1 Retiming and Sequential SER
100(3)
6.2.2 Retiming and Random-Pattern Testability
103(1)
6.3 Retiming by Linear Programs
104(3)
6.3.1 Minimum-Observability Retiming
104(2)
6.3.2 Incorporating Register Sharing
106(1)
6.4 Empirical Validation
107(8)
References
113(2)
7 Summary and Extensions
115(6)
7.1 Summary
115(1)
7.2 Future Directions
116(3)
7.2.1 Process Variations and Aging Effects
116(1)
7.2.2 Analysis of Biological Systems
117(2)
7.3 Concluding Remarks
119(2)
References
120(1)
Index 121