This book describes novel and disruptive architecture and circuit design techniques, toward the realization of low-power, standard-compliant radio architectures and silicon implementation of the circuits required for a variety of leading-edge applications. Readers will gain an understanding of the circuit level challenges that exist for low power radios, compatible with the IEEE 802.15.6 standard. The authors discuss current techniques to address some of these challenges, helping readers to understand the state-of-the-art, and to address the various, open research problems that exist with respect to realizing low power radios.
- Enables readers to face challenging bottleneck in low power radio design, with state-of-the-art, circuit-level design techniques;
- Provides readers with basic knowledge of circuits suitable for low power radio circuits compatible with the IEEE 802.15.6 standard;
- Discusses new and emerging architectures and circuit techniques, enabling applications such as body area networks and internet of things.
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1 | (4) |
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4 | (1) |
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4 | (1) |
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5 | (18) |
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5 | (1) |
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6 | (1) |
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2.3 Transmitter Specifications |
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7 | (3) |
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2.3.1 System Level Specifications |
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7 | (1) |
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2.3.2 Circuit Level Specifications |
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8 | (2) |
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10 | (5) |
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15 | (1) |
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2.6 Process Variation and Device Mismatches |
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16 | (1) |
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17 | (3) |
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20 | (1) |
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21 | (2) |
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23 | (18) |
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23 | (1) |
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24 | (1) |
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3.3 Receiver Specifications |
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25 | (2) |
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3.3.1 System Level Specifications |
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26 | (1) |
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3.3.2 Circuit Level Specifications |
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26 | (1) |
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27 | (7) |
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28 | (1) |
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29 | (1) |
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3.4.3 Noise Cancellation Ratio |
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29 | (4) |
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33 | (1) |
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3.5 Noise Cancellation Simulations |
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34 | (1) |
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3.6 Impact of Process Variation |
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34 | (1) |
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35 | (4) |
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39 | (1) |
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39 | (2) |
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4 Dual-Path Noise Cancelling LNA |
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41 | (16) |
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41 | (3) |
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44 | (3) |
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4.2.1 CS Noise Cancellation |
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44 | (2) |
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4.2.2 CG Noise Cancellation |
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46 | (1) |
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46 | (1) |
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4.3 Signal, Noise, and Nonlinearity Analysis |
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47 | (3) |
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47 | (1) |
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48 | (1) |
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4.3.3 Nonlinearity Analysis |
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49 | (1) |
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4.4 Impact of Process Variation |
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50 | (1) |
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50 | (5) |
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55 | (1) |
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55 | (2) |
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57 | (10) |
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57 | (1) |
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58 | (1) |
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58 | (2) |
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60 | (4) |
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64 | (1) |
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65 | (2) |
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67 | (2) |
| Index |
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69 | |
Mustafijur Rahman is a Research Scientist at Intel Labs, Hillsboro, Oregon where he is working on advanced transceiver architectures and synthesizers. His research interest is in the field of radio frequency/mmWave integrated circuit design. He has worked as Senior Hardware Engineer at Qualcomm Atheros Inc., San Jose, California during 2016 to 2017. He received the M.S. and Ph.D. degrees in Electrical Engineering from the University of Minnesota, Twin Cities in 2014 and 2016 respectively. During his PhD he has designed IEEE 802.15.6 compliant low power 2.4 GHz transceiver for Wireless Body Area Networks. He has top to bottom level radio frequency integrated circuit design experience i.e. from system level standard specifications to circuit level implementation. He was the recipient of the University of Minnesota Doctoral Dissertation Fellowship 2015, the Best in Session Awards at TECHCON 2014, 2015, and 2016, and the Gold Medal for the Best Engineering Graduate 2009 at NIT Silchar.
Ramesh Harjani received the B.S. degree from the Birla Institute of Technology and Science, Pilani, India, in 1982, the M.S. degree from IIT Delhi, New Delhi, India, in 1984, and the Ph.D. degree from Carnegie Mellon University, Pittsburgh, PA, USA, in 1989, all in electrical engineering. In 2001, he co-founded Bermai, Inc., Palo Alto, CA, USA, a startup company developing CMOS chips for wireless multimedia applications. Prior to joining the University of Minnesota, he was with Mentor Graphics Corporation, San Jose, CA, USA. He has been a Visiting Professor with Lucent Bell Labs, Allentown, PA, USA, and the Army Research Labs, Adelphi, MD, USA. He is currently the Edgar F. Johnson Professor with the Department of Electrical and Computer Engineering, University of Minnesota. His current research interests include analog/RF circuits for communications. Dr. Harjani received the National Science Foundation Research Initiation Award in 1991 and the Best Paper Awards at the 1987 IEEE/ACM Design Automation Conference, the 1989 International Conference on Computer-Aided Design, the 1998 GOMAC, and the 2007, 2010, and 2012 TECHCONs. His research group was a recipient of the SRC Copper Design Challenge in 2000 and the SRC SiGe challenge in 2003. He was the Technical Program Chair of the IEEE Custom Integrated Circuits Conference from 2013 to 2014. He was the Chair of the IEEE Circuits and Systems Society Technical Committee on Analog Signal Processing from 1999 to 2000 and a Distinguished Lecturer of the IEEE Circuits and Systems Society from 2001 to 2002. He was an Associate Editor of the IEEE Transactions on Circuits and Systems II from 1995 to 1997, a Guest Editor of the International Journal of High-Speed Electronics and Systems and Analog Integrated Circuits and Signal Processing in 2004, and a Guest Editor of the IEEE Journal of Solid-State Circuits from 2009 to 2011. He was a Senior Editor of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems from 2011 to 2013.
