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Design of Very High-Frequency Multirate Switched-Capacitor Circuits: Extending the Boundaries of CMOS Analog Front-End Filtering 1st ed. Softcover of orig. ed. 2006 [Pehme köide]

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Design of Very High-Frequency Multirate Switched-Capacitor Circuits: Extending the Boundaries of CMOS Analog Front-End Filtering 1st ed. Softcover of orig. ed. 2006Suurem pilt
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Püsilink: https://www.kriso.ee/db/9781441938671.html
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Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed:

-Optimum circuit architecture tradeoff analysis
-Simple speed and power trade-off analysis of active elements
-High-order filtering response accuracy with respect to capacitor-ratio mismatches
-Time-interleaved effect with respect to gain and offset mismatch
-Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding
-Stage noise analysis and allocation scheme
-Substrate and supply noise reduction
-Gain-and offset-compensation techniques
-High-bandwidth low-power amplifier design and layout
-Very low timing-skew multiphase generation

Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.

Dedication v
Preface xiii
Acknowledgment xvii
List of Abbreviations
xix
List of Figures
xxiii
List of Tables
xxxi
1 Introduction
1(14)
1 High-Frequency Integrated Analog Filtering
1(2)
2 Multirate Switched-Capacitor Circuit Techniques
3(2)
3 Sampled-Data Interpolation Techniques
5(3)
4 Research Goals and Design Challenges
8(7)
2 Improved Multirate Polyphase-Based Interpolation Structures
15(26)
1 Introduction
15(1)
2 Conventional and Improved Analog Interpolation
16(4)
3 Polyphase Structures for Optimum-class Improved Analog Interpolation
20(2)
4 Multirate ADB Polyphase Structures
22(4)
4.1 Canonic and Non-Canonic ADB Realizations
22(1)
4.1.1 FIR System Response
22(2)
4.1.2 MR System Response
24(2)
4.2 SC Circuit Architectures
26(7)
5 Low-Sensitivity Multirate IIR Structures
33(4)
5.1 Mixed Cascade/Parallel Form
33(4)
5.2 Extra-Ripple IIR Form
37(1)
6 Summary
37(4)
3 Practical Multirate SC Circuit Design Considerations
41(28)
1 Introduction
41(1)
2 Power Consumption Analysis
41(3)
3 Capacitor-Ratio Sensitivity Analysis
44(1)
3.1 FIR Structure
44(2)
3.2 IIR Structure
46(3)
4 Finite Gain & Bandwidth Effects
49(1)
5 Input-Referred Offset Effects
49(6)
6 Phase Timing-Mismatch Effects
55(4)
6.1 Periodic Fixed Timing-Skew Effect
55(4)
6.2 Random Timing-Jitter Effects
59(1)
7 Noise Analysis
59(6)
8 Summary
65(4)
4 Gain- and Offset-Compensation for Multirate SC Circuits
69(30)
1 Introduction
69(1)
2 Autozeroing and Correlated-Double Sampling Techniques
70(2)
3 AZ and CDS SC Delay Blocks with Mismatch-Free Property
72(10)
3.1 SC Delay Block Architectures
72(5)
3.2 Gain and Offset Errors -- Expressions and Simulation Verification
77(3)
3.3 Multi-Unit Delay Implementations
80(2)
4 AZ and CDS SC Accumulators
82(2)
4.1 SC Accumulator Architectures
82(1)
4.2 Gain and Offset Errors -- Expressions and Simulation Verification
82(2)
5 Design Examples
84(5)
6 Speed and Power Considerations
89(5)
7 Summary
94(5)
5 Design of a 108 MHz Multistage SC Video Interpolating Filter
99(24)
1 Introduction
99(2)
2 Optimum Architecture Design
101(1)
2.1 Multistage Polyphase Structure with Half-Band Filtering
101(1)
2.2 Spread-Reduction Scheme
102(1)
2.3 Coefficient-Sharing Techniques
103(3)
3 Circuit Design
106(7)
3.1 1st-Stage
106(3)
3.2 2nd- and 3rd-Stage
109(2)
3.3 Digital Clock Phase Generation
111(2)
4 Circuit Layout
113(1)
5 Simulation Results
114(4)
5.1 Behavioral Simulations
114(1)
5.2 Circuit-Level Simulations
115(3)
6 Summary
118(5)
6 Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter
123(40)
1 Introduction
123(2)
2 Prototype System-Level Design
125(3)
2.1 Multi-notch FIR Transfer Function
125(2)
2.2 Time-Interleaved Serial ADB Polyphase Structure with Autozeroing
127(1)
3 Prototype Circuit-Level Design
128(15)
3.1 Autozeroing ADB and Accumulator
128(2)
3.2 High-Speed Multiplexer
130(3)
3.3 Overall SC Circuit Architecture
133(1)
3.4 Telescopic opamp with Wide-Swing Biasing
133(3)
3.5 nMOS Switches
136(1)
3.6 Noise Calculation
137(1)
3.7 I/O Circuitry
138(1)
3.8 Low Timing-Skew Clock Generation
138(5)
4 Layout Considerations
143(9)
4.1 Device and Path Matching
143(4)
4.2 Substrate and Supply Noise Decoupling
147(4)
4.3 Shielding
151(1)
4.4 Floor Plan
151(1)
5 Simulation Results
152(6)
5.1 Opamp Simulations
152(3)
5.2 Filter Behavioral Simulations
155(1)
5.3 Filter Transistor-Level and Post-Layout Simulations
156(2)
6 Summary
158(5)
7 Experimental Results
163(24)
1 Introduction
163(1)
2 PCB Design
163(6)
2.1 Floor Plan
164(3)
2.2 Power Supplies and Decoupling
167(1)
2.3 Biasing Currents
167(1)
2.4 Input and Output Network
167(2)
3 Measurement Setup and Results
169(12)
3.1 Frequency Response
170(2)
3.2 Time-Domain Signal Waveforms
172(1)
3.3 One-Tone Signal Spectrum
172(2)
3.4 Two-Tone Intermodulation Distortion
174(3)
3.5 THD and IM3 vs. Input Signal Level
177(1)
3.6 Noise Performance
177(3)
3.7 CMRR and PSRR
180(1)
4 Summary
181(6)
8 Conclusions
187(4)
APPENDIX 1 TIMING-MISMATCH ERRORS WITH NONUNIFORMLY HOLDING EFFECTS
191(24)
1 Spectrum Expressions for IU-ON(SH) and IN-CON(SH)
193(4)
1.1 IU-ON(SH)
193(4)
1.2 IN-CON(SH)
197(1)
2 Closed Form SINAD Expression for IU-ON(SH) and IN-CON(SH)
197(6)
2.1 IU-ON(SH)
198(3)
2.2 IN-CON(SH)
201(2)
3 Closed Form SFDR Expression for IN-CON(SH) systems
203(2)
4 Spectrum Correlation of IN-OU(IS) and IU-ON(SH)
205(10)
APPENDIX 2 NOISE ANALYSIS FOR SC ADB DELAY LINE AND POLYPHASE SUBFDLTERS
215(6)
1 Output Noise of ADB Delay Line
215(2)
2 Output Noise of Polyphase Subfilters
217(4)
2.1 Using TSI Input Coefficient SC Branches
217(3)
2.2 Using OFR Input Coefficient SC Branches
220(1)
APPENDIX 3 GAIN, PHASE AND OFFSET ERRORS FOR GOC MF SC DELAY CIRCUIT I AND J
221
1 GOC MF SC Delay Circuit I
221(4)
2 GOC MF SC Delay Circuit J
225