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Digital Design and Computer Architecture, RISC-V Edition [Pehme köide]

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(Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USA), (Assistant Professor of Engineering, Harvey Mudd College, Claremont, CA, USA)
  • Formaat: Paperback / softback, 592 pages, kõrgus x laius: 235x191 mm, kaal: 870 g, Approx. 500 illustrations; Illustrations
  • Ilmumisaeg: 03-Nov-2021
  • Kirjastus: Morgan Kaufmann Publishers In
  • ISBN-10: 0128200642
  • ISBN-13: 9780128200643
Teised raamatud teemal:
Digital Design and Computer Architecture, RISC-V EditionSuurem pilt
  • Formaat: Paperback / softback, 592 pages, kõrgus x laius: 235x191 mm, kaal: 870 g, Approx. 500 illustrations; Illustrations
  • Ilmumisaeg: 03-Nov-2021
  • Kirjastus: Morgan Kaufmann Publishers In
  • ISBN-10: 0128200642
  • ISBN-13: 9780128200643
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780128200643.html
Märksõnad:

The newest addition to the Harris and Harris family of Digital Design and Computer Architecture books, this RISC-V Edition covers the fundamentals of digital logic design and reinforces logic concepts through the design of a RISC-V microprocessor. Combining an engaging and humorous writing style with an updated and hands-on approach to digital design, this book takes the reader from the fundamentals of digital logic to the actual design of a processor. By the end of this book, readers will be able to build their own RISC-V microprocessor and will have a top-to-bottom understanding of how it works.

Beginning with digital logic gates and progressing to the design of combinational and sequential circuits, this book uses these fundamental building blocks as the basis for designing a RISC-V processor. SystemVerilog and VHDL are integrated throughout the text in examples illustrating the methods and techniques for CAD-based circuit design. The companion website includes a chapter on I/O systems with practical examples that show how to use SparkFun’s RED-V RedBoard to communicate with peripheral devices such as LCDs, Bluetooth radios, and motors.

This book will be a valuable resource for students taking a course that combines digital logic and computer architecture or students taking a two-quarter sequence in digital logic and computer organization/architecture.

  • Covers the fundamentals of digital logic design and reinforces logic concepts through the design of a RISC-V microprocessor
  • Gives students a full understanding of the RISC-V instruction set architecture, enabling them to build a RISC-V processor and program the RISC-V processor in hardware simulation, software simulation, and in hardware
  • Includes both SystemVerilog and VHDL designs of fundamental building blocks as well as of single-cycle, multicycle, and pipelined versions of the RISC-V architecture
  • Features a companion website with a bonus chapter on I/O systems with practical examples that show how to use SparkFun’s RED-V RedBoard to communicate with peripheral devices such as LCDs, Bluetooth radios, and motors
  • The companion website also includes appendices covering practical digital design issues and C programming as well as links to CAD tools, lecture slides, laboratory projects, and solutions to exercises
  • See the companion EdX MOOCs ENGR85A and ENGR85B with video lectures and interactive problems
Preface xix
Features xx
Online Supplements xxi
How to Use the Software Tools in a Course xxii
Labs xxiii
RVfpga xxiii
Bugs xxiv
Acknowledgments xxiv
About the Authors xxv
Chapter 1 From Zero to One
1(52)
1.1 The Game Plan
1(1)
1.2 The Art of Managing Complexity
2(3)
1.2.1 Abstraction
2(1)
1.2.2 Discipline
3(1)
1.2.3 The Three-Y's
4(1)
1.3 The Digital Abstraction
5(2)
1.4 Number Systems
7(10)
1.4.1 Decimal Numbers
7(1)
1.4.2 Binary Numbers
7(2)
1.4.3 Hexadecimal Numbers
9(2)
1.4.4 Bytes, Nibbles, and All That Jazz
11(1)
1.4.5 Binary Addition
12(1)
1.4.6 Signed Binary Numbers
13(4)
1.5 Logic Gates
17(3)
1.5.1 NOT Gate
18(1)
1.5.2 Buffer
18(1)
1.5.3 AND Gate
18(1)
1.5.4 OR Gate
19(1)
1.5.5 Other Two-Input Gates
19(1)
1.5.6 Multiple-Input Gates
19(1)
1.6 Beneath the Digital Abstraction
20(4)
1.6.1 Supply Voltage
20(1)
1.6.2 Logic Levels
20(1)
1.6.3 Noise Margins
21(1)
1.6.4 DC Transfer Characteristics
22(1)
1.6.5 The Static Discipline
22(2)
1.7 CMOS Transistors
24(8)
1.7.1 Semiconductors
25(1)
1.7.2 Diodes
25(1)
1.7.3 Capacitors
26(1)
1.7.4 nMOS and pMOS Transistors
26(3)
1.7.5 CMOS NOT Gate
29(1)
1.7.6 Other CMOS Logic Gates
29(2)
1.7.7 Transmission Gates
31(1)
1.7.8 Pseudo-nMOS Logic
31(1)
1.8 Power Consumption
32(2)
1.9 Summary and a Look Ahead
34(19)
Exercises
36(14)
Interview Questions
50(3)
Chapter 2 Combinational Logic Design
53(54)
2.1 Introduction
53(3)
2.2 Boolean Equations
56(2)
2.2.1 Terminology
56(1)
2.2.2 Sum-of-Products Form
56(2)
2.2.3 Product-of-Sums Form
58(1)
2.3 Boolean Algebra
58(6)
2.3.1 Axioms
59(1)
2.3.2 Theorems of One Variable
59(1)
2.3.3 Theorems of Several Variables
60(2)
2.3.4 The Truth Behind It All
62(1)
2.3.5 Simplifying Equations
63(1)
2.4 From Logic to Gates
64(3)
2.5 Multilevel Combinational Logic
67(4)
2.5.1 Hardware Reduction
68(1)
2.5.2 Bubble Pushing
69(2)
2.6 X's and Z's, Oh My
71(2)
2.6.1 Illegal Value: X
71(1)
2.6.2 Floating Value: Z
72(1)
2.7 Karnaugh Maps
73(8)
2.7.1 Circular Thinking
74(1)
2.7.2 Logic Minimization with K-Maps
75(4)
2.7.3 Don't Cares
79(1)
2.7.4 The Big Picture
80(1)
2.8 Combinational Building Blocks
81(5)
2.8.1 Multiplexers
81(3)
2.8.2 Decoders
84(2)
2.9 Timing
86(7)
2.9.1 Propagation and Contamination Delay
86(4)
2.9.2 Glitches
90(3)
2.10 Summary
93(14)
Exercises
95(9)
Interview Questions
104(3)
Chapter 3 Sequential Logic Design
107(64)
3.1 Introduction
107(1)
3.2 Latches and Flip-Flops
107(10)
3.2.1 SR Latch
109(2)
3.2.2 D Latch
111(1)
3.2.3 D Flip-Flop
112(1)
3.2.4 Register
112(1)
3.2.5 Enabled Flip-Flop
113(1)
3.2.6 Resettable Flip-Flop
114(1)
3.2.7 Transistor-Level Latch and Flip-Flop Designs
114(2)
3.2.8 Putting It All Together
116(1)
3.3 Synchronous Logic Design
117(4)
3.3.1 Some Problematic Circuits
117(1)
3.3.2 Synchronous Sequential Circuits
118(2)
3.3.3 Synchronous and Asynchronous Circuits
120(1)
3.4 Finite State Machines
121(18)
3.4.1 FSM Design Example
121(6)
3.4.2 State Encodings
127(3)
3.4.3 Moore and Mealy Machines
130(2)
3.4.4 Factoring State Machines
132(3)
3.4.5 Deriving an FSM from a Schematic
135(3)
3.4.6 FSM Review
138(1)
3.5 Timing of Sequential Logic
139(16)
3.5.1 The Dynamic Discipline
140(1)
3.5.2 System Timing
140(6)
3.5.3 Clock Skew
146(3)
3.5.4 Metastability
149(1)
3.5.5 Synchronizers
150(2)
3.5.6 Derivation of Resolution Time
152(3)
3.6 Parallelism
155(4)
3.7 Summary
159(12)
Exercises
160(9)
Interview Questions
169(2)
Chapter 4 Hardware Description Languages
171(66)
4.1 Introduction
171(4)
4.1.1 Modules
171(1)
4.1.2 Language Origins
172(1)
4.1.3 Simulation and Synthesis
173(2)
4.2 Combinational Logic
175(13)
4.2.1 Bitwise Operators
175(3)
4.2.2 Comments and White Space
178(1)
4.2.3 Reduction Operators
178(1)
4.2.4 Conditional Assignment
179(1)
4.2.5 Internal Variables
180(2)
4.2.6 Precedence
182(1)
4.2.7 Numbers
183(1)
4.2.8 Z'sandX's
184(2)
4.2.9 BitSwizzling
186(1)
4.2.10 Delays
186(2)
4.3 Structural Modeling
188(3)
4.4 Sequential Logic
191(5)
4.4.1 Registers
191(1)
4.4.2 Resettable Registers
192(2)
4.4.3 Enabled Registers
194(1)
4.4.4 Multiple Registers
195(1)
4.4.5 Latches
196(1)
4.5 More Combinational Logic
196(11)
4.5.1 Case Statements
199(1)
4.5.2 If Statements
200(3)
4.5.3 Truth Tables with Don't Cares
203(1)
4.5.4 Blocking and Nonblocking Assignments
203(4)
4.6 Finite State Machines
207(4)
4.7 Data Types
211(4)
4.7.1 SystemVerilog
212(1)
4.7.2 VHDL
213(2)
4.8 Parameterized Modules
215(3)
4.9 Testbenches
218(4)
4.10 Summary
222(15)
Exercises
224(11)
Interview Questions
235(2)
Chapter 5 Digital Building Blocks
237(62)
5.1 Introduction
237(1)
5.2 Arithmetic Circuits
237(19)
5.2.1 Addition
237(7)
5.2.2 Subtraction
244(1)
5.2.3 Comparators
245(2)
5.2.4 ALU
247(4)
5.2.5 Shifters and Rotators
251(2)
5.2.6 Multiplication
253(1)
5.2.7 Division
254(1)
5.2.8 Further Reading
255(1)
5.3 Number Systems
256(5)
5.3.1 Fixed-Point Number Systems
256(1)
5.3.2 Floating-Point Number Systems
257(4)
5.4 Sequential Building Blocks
261(4)
5.4.1 Counters
261(1)
5.4.2 Shift Registers
262(3)
5.5 Memory Arrays
265(7)
5.5.1 Overview
265(2)
5.5.2 Dynamic Random Access Memory (DRAM)
267(1)
5.5.3 Static Random Access Memory (SRAM)
268(1)
5.5.4 Area and Delay
268(1)
5.5.5 Register Files
269(1)
5.5.6 Read Only Memory (ROM)
269(2)
5.5.7 Logic Using Memory Arrays
271(1)
5.5.8 Memory HDL
272(1)
5.6 Logic Arrays
272(11)
5.6.1 Programmable Logic Array (PLA)
275(1)
5.6.2 Field Programmable Gate Array (FPGA)
276(6)
5.6.3 Array Implementations
282(1)
5.7 Summary
283(16)
Exercises
285(12)
Interview Questions
297(2)
Chapter 6 Architecture
299(94)
6.1 Introduction
299(1)
6.2 Assembly Language
300(8)
6.2.1 Instructions
301(1)
6.2.2 Operands: Registers, Memory, and Constants
302(6)
6.3 Programming
308(24)
6.3.1 Program Flow
308(1)
6.3.2 Logical, Shift, and Multiply Instructions
308(3)
6.3.3 Branching
311(2)
6.3.4 Conditional Statements
313(2)
6.3.5 Getting Loopy
315(2)
6.3.6 Arrays
317(3)
6.3.7 Function Calls
320(10)
6.3.8 Pseudoinstructions
330(2)
6.4 Machine Language
332(12)
6.4.1 R-Type Instructions
332(2)
6.4.2 /-Type Instructions
334(2)
6.4.3 S/B-Type Instructions
336(2)
6.4.4 U/J-Type Instructions
338(2)
6.4.5 Immediate Encodings
340(1)
6.4.6 Addressing Modes
341(1)
6.4.7 Interpreting Machine Language Code
342(1)
6.4.8 The Power of the Stored Program
343(1)
6.5 Lights, Camera, Action: Compiling, Assembling, and Loading
344(11)
6.5.1 The Memory Map
344(2)
6.5.2 Assembler Directives
346(2)
6.5.3 Compiling
348(2)
6.5.4 Assembling
350(3)
6.5.5 Linking
353(2)
6.5.6 Loading
355(1)
6.6 Odds and Ends
355(8)
6.6.1 Endianness
355(1)
6.6.2 Exceptions
356(4)
6.6.3 Signed and Unsigned Instructions
360(1)
6.6.4 Floating-Point Instructions
361(1)
6.6.5 Compressed Instructions
362(1)
6.7 Evolution of the RISC-V Architecture
363(3)
6.7.1 RISC-V Base Instruction Sets and Extensions
364(1)
6.7.2 Comparison of RISC-V and MIPS Architectures
365(1)
6.7.3 Comparison of RISC-V and ARM Architectures
365(1)
6.8 Another Perspective: x86 Architecture
366(8)
6.8.1 x86 Registers
366(1)
6.8.2 x86 Operands
367(2)
6.8.3 Status Flags
369(1)
6.8.4 x86 Instructions
369(2)
6.8.5 x86 Instruction Encoding
371(1)
6.8.6 Other x86 Peculiarities
372(1)
6.8.7 The Big Picture
373(1)
6.9 Summary
374(19)
Exercises
375(15)
Interview Questions
390(3)
Chapter 7 Microarchitecture
393(106)
7.1 Introduction
393(4)
7.1.1 Architectural State and Instruction Set
393(1)
7.1.2 Design Process
394(2)
7.1.3 Microarchitectures
396(1)
7.2 Performance Analysis
397(1)
7.3 Single-Cycle Processor
398(17)
7.3.1 Sample Program
399(1)
7.3.2 Single-Cycle Datapath
399(8)
7.3.3 Single-Cycle Control
407(3)
7.3.4 More Instructions
410(2)
7.3.5 Performance Analysis
412(3)
7.4 Multicycle Processor
415(24)
7.4.1 Multicycle Datapath
416(6)
7.4.2 Multicycle Control
422(10)
7.4.3 More Instructions i
432(3)
7.4.4 Performance Analysis
435(4)
7.5 Pipelined Processor
439(17)
7.5.1 Pipelined Datapath
441(2)
7.5.2 Pipelined Control
443(1)
7.5.3 Hazards
443(11)
7.5.4 Performance Analysis
454(2)
7.6 HDL Representation
456(12)
7.6.1 Single-Cycle Processor
457(4)
7.6.2 Generic Building Blocks
461(3)
7.6.3 Testbench
464(4)
7.7 Advanced Microarchitecture
468(14)
7.7.1 Deep Pipelines
468(1)
7.7.2 Micro-Operations
469(1)
7.7.3 Branch Prediction
470(2)
7.7.4 Superscalar Processors
472(1)
7.7.5 Out-of-Order Processor
473(3)
7.7.6 Register Renaming
476(2)
7.7.7 Multithreading
478(1)
7.7.8 Multiprocessors
479(3)
7.8 Real-World Perspective: Evolution of RISC-V Microarchitecture
482(4)
7.9 Summary
486(13)
Exercises
488(9)
Interview Questions
497(2)
Chapter 8 Memory Systems
499(43)
8.1 Introduction
499(4)
8.2 Memory System Performance Analysis
503(2)
8.3 Caches
505(14)
8.3.1 What Data is Held in the Cache?
505(1)
8.3.2 How is Data Found?
506(8)
8.3.3 What Data is Replaced?
514(1)
8.3.4 Advanced Cache Design
515(4)
8.4 Virtual Memory
519(11)
8.4.1 Address Translation
522(1)
8.4.2 The Page Table
523(2)
8.4.3 The Translation Lookaside Buffer
525(1)
8.4.4 Memory Protection
526(1)
8.4.5 Replacement Policies
527(1)
8.4.6 Multilevel Page Tables
527(3)
8.5 Summary
530(12)
Epilogue
530(2)
Exercises
532(9)
Interview Questions
541(1)
Chapter 9 Embedded I/O Systems
542(1)
9.1 Introduction
542(1)
Chapter 9 Is Available as an online supplement
542(1)
9.1 Introduction
542(1)
9.2 Memory-Mapped I/O
542(1)
9.3 Embedded I/O Systems
542(1)
9.3.1 RED-V Board
542(1)
9.3.2 FE310-G002 System-on-Chip
542(1)
9.3.3 General-Purpose Digital I/O
542(1)
9.3.4 Device Drivers
542(1)
9.3.5 Serial I/O
542(1)
9.3.6 Timers
542(1)
9.3.7 Analog I/O
542(1)
9.3.8 Interrupts
542(1)
9.4 Other Microcontroller Peripherals
542(1)
9.4.1 Character LCDs
542(1)
9.4.2 VGA Monitor
542(1)
9.4.3 Bluetooth Wireless Communication
542(1)
9.4.4 Motor Control
542(1)
9.5 Summary
542(1)
Appendix A Digital System Implementation
543(1)
A.1 Introduction
543(1)
Appendix A is available as an online supplement
543(1)
A.1 Introduction
543(1)
A.2 74xx Logic
543(1)
A.2.1 Logic Gates
543(1)
A.2.2 Other Functions
543(1)
A.3 Programmable Logic
543(1)
A.3.1 PROMs
543(1)
A.3.2 PLAs
543(1)
A.3.3 FPGAs
543(1)
A.4 Application-Specific Integrated Circuits
543(1)
A.5 Datasheets
543(1)
A.6 Logic Families
543(1)
A.7 Switches and Light-Emitting Diodes
543(1)
A.7.1 Switches
543(1)
A.7.2 LEDs
543(1)
A.8 Packaging and Assembly
543(1)
A.8.1 Packages
543(1)
A.8.2 Breadboards
543(1)
A.8.3 Printed Circuit Boards
543(1)
A.8.4 Putting It All Together
543(1)
A.9 Transmission Lines
543(1)
A.9.1 Matched Termination
543(1)
A.9.2 Open Termination
543(1)
A.9.3 Short Termination
543(1)
A.9.4 Mismatched Termination
543(1)
A.9.5 When to Use Transmission Line Models
543(1)
A.9.6 Proper Transmission Line Terminations
543(1)
A.9.7 Derivation of Z0
543(1)
A.9.8 Derivation of the Reflection Coefficient
543(1)
A.9.9 Putting It All Together
543(1)
A.10 Economics
543(1)
Appendix B RISC-V Instruction Set Summary
544(1)
Appendix C C Programming
545(1)
C.1 Introduction
545(1)
Appendix C Is Available as an online supplement
545(2)
C.1 Introduction
545(1)
C.2 Welcome to C
545(1)
C.2.1 C Program Dissection
545(1)
C.2.2 Running a C Program
545(1)
C.3 Compilation
545(1)
C.3.1 Comments
545(1)
C.3.2 #define
545(1)
C.3.3 #include
545(1)
C.4 Variables
545(1)
C.4.1 Primitive Data Types
545(1)
C.4.2 Global and Local Variables
545(1)
C.4.3 Initializing Variables
545(1)
C.5 Operators
545(1)
C.6 Function Calls
545(1)
C.7 Control-Flow Statements
545(1)
C.7.1 Conditional Statements
545(1)
C.7.2 Loops
545(1)
C.8 More Data Types
545(1)
C.8.1 Pointers
545(1)
C.8.2 Arrays
545(1)
C.8.3 Characters
545(1)
C.8.4 Strings
545(1)
C.8.5 Structures
545(1)
C.8.6 typedef
545(1)
C.8.7 Dynamic Memory Allocation
545(1)
C.8.8 Linked Lists
545(1)
C.9 Standard Libraries
545(1)
C.9.1 stdio
545(1)
C.9.2 stdlib
545(1)
C.9.3 math
545(1)
C.9.4 string
545(1)
C.10 Compiler and Command Line Options
545(1)
C.10.1 Compiling Multiple C Source Files
545(1)
C.10.2 Compiler Options
545(1)
C.10.3 Command Line Arguments
545(1)
C.11 Common Mistakes
545(2)
Further Reading 547(2)
Index 549
Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing. Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future. David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.