Digital Design with CPLD Applications and VHDL 2nd edition [Multiple-component retail product, part(s) enclosed]

Preface		ix
Basic Principles of Digital Systems		2	(28)
Digital Versus Analog Electronics		4	(1)
Digital Logic Levels		5	(1)
The Binary Number System		6	(8)
Hexadecimal Numbers		14	(4)
Digital Waveforms		18	(12)
Logic Functions and Gates		30	(40)
Basic Logic Functions		32	(6)
Derived Logic Functions		38	(4)
DeMorgan's Theorems and Gate Equivalence		42	(3)
Logic Switches and LED Indicators		45	(3)
Enable and Inhibit Properties of Logic Gates		48	(7)
Integrated Circuit Logic Gates		55	(15)
Boolean Algebra and Combinational Logic		70	(94)
Boolean Expressions, Logic Diagrams, and Truth Tables		72	(8)
Sum-of-Products and Product-of-Sums Forms		80	(6)
Theorems of Boolean Algebra		86	(14)
Simplifying SOP and POS Expressions		100	(4)
Simplification by the Karnaugh Map Method		104	(16)
Simplification by DeMorgan Equivalent Gates		120	(2)
Universal Property of NAND/NOR Gates		122	(6)
Practical Circuit Implementation in SSI Logic		128	(3)
Pulsed Operation of Logic Circuits		131	(2)
A General Approach to Logic Circuit Design		133	(31)
Introduction to PLDs and Quartus II		164	(68)
What is a PLD?		166	(3)
Programmable Sum-of-Products Arrays		169	(2)
PAL Fuse Matrix and Combinational Outputs		171	(4)
PAL Outputs with Programmable Polarity		175	(3)
Programming CPLDs Using Quartus II		178	(4)
Quartus II Design Flow and Graphical User Interface		182	(3)
Creating a Quartus II Project and Block Diagram File		185	(10)
Compiling and Simulating a Design in Quartus II		195	(10)
Transferring a Design to a Target CPLD		205	(11)
Using the Quartus II Block Editor to Create a Hierarchical Design		216	(16)
Introduction to VHDL		232	(34)
VHDL Basics		234	(3)
Making a VHDL File in Quartus II		237	(7)
VHDL Syntax for Port, Mode, and Type		244	(10)
Signals in VHDL		254	(12)
Combinational Logic Functions		266	(80)
Decoders		268	(23)
Encoders		291	(6)
Multiplexers		297	(16)
Demultiplexers		313	(5)
Magnitude Comparators		318	(7)
Parity Generators and Checkers		325	(21)
Digital Arithmetic and Arithmetic Circuits		346	(62)
Digital Arithmetic		348	(3)
Representing Signed Binary Numbers		351	(2)
Signed Binary Arithmetic		353	(7)
Hexadecimal Arithmetic		360	(2)
Numeric and Alphanumeric Codes		362	(5)
Binary Adders and Subtractors		367	(21)
BCD Adders		388	(5)
Carry Generation in Quartus II		393	(15)
Introduction to Sequential Logic		408	(92)
Latches		411	(3)
NAND/NOR Latches		414	(15)
Gated Latches		429	(18)
Edge-Triggered D Flip-Flops		447	(5)
Edge-Triggered JK Flip-Flops		452	(8)
Edge-Triggered T Flip-Flops		460	(2)
Flip-Flops in PLDs (Registered Outputs)		462	(5)
Generic Array Logic		467	(4)
Max 7000s CPLD		471	(2)
Flex 10K CPLD		473	(27)
Counters and Shift Registers		500	(126)
Basic Concepts of Digital Counters		503	(5)
Synchronous Counters		508	(6)
Design of Synchronous Counters		514	(9)
Programming Binary Counters for CPLDs		523	(11)
Control Options for Synchronous Counters		534	(18)
Programming Presettable and Bidirectional Counters for CPLDs		552	(23)
Shift Registers		575	(14)
Programming Shift Registers in VHDL		589	(12)
Shift Register Counters		601	(25)
State Machine Design		626	(42)
State Machines		628	(1)
State Machines with No Control Inputs		629	(7)
State Machines with Control Inputs		636	(9)
Switch Debouncer for a Normally Open Pushbutton Switch		645	(8)
Unused States in State Machines		653	(6)
Traffic Light Controller		659	(9)
Logic Gate Circuitry		668	(76)
Electrical Characteristics of Logic Gates		670	(4)
Propagation Delay		674	(2)
Flip-Flop Timing Parameters		676	(3)
Fanout		679	(5)
Power Dissipation		684	(4)
Noise Margin		688	(2)
Interfacing TTL and CMOS Gates		690	(3)
Internal Circuitry of TTL Gates		693	(21)
Internal Circuitry of CMOS Gates		714	(12)
TTL and CMOS Variations		726	(18)
Interfacing Analog and Digital Circuits		744	(84)
Analog and Digital Signals		746	(15)
Digital-to-Analog Conversion		761	(19)
Analog-to-Digital Conversion		780	(25)
Data Acquisition		805	(23)
Memory Devices and Systems		828	(36)
Basic Memory Concepts		830	(8)
Random Access Read/Write Memory (RAM)		838	(6)
Read Only Memory (ROM)		844	(7)
Sequential Memory: FIFO and LIFO		851	(2)
Dynamic RAM Modules		853	(2)
Memory Systems		855	(9)
Introduction to Microprocessors		864	(91)
Basic Structure of a Microcomputer		866	(4)
Register Level Structure of a Microcomputer System		870	(15)
Tristate Busses in Altera CPLDs		885	(11)
Quartus II Implementation of the RISC8v1 MCU		896	(18)
Creating New Instructions (RISC8v2)		914	(3)
Branch Instructions (RISC8v3)		917	(5)
RISC8 Test Circuit		922	(2)
Possible Enhancements to RISC8v3 MCU		924	(13)
Appendices
Appendix A Converting MAX+PLUS II Projects to Quartus II		937	(18)
Answers to Selected Odd-Numbered Problems		955	(42)
Index		997

Robert Dueck received his B.Sc. degree in electrical engineering from the University of Manitoba in Winnipeg, Canada, and worked for several years as a design engineer at Motorola Canada in Toronto. He began teaching in 1986, specializing in digital and microcomputer subjects in the Electronics and Computer Engineering Technology programs at Seneca College in Toronto. His first book, Fundamentals of Digital Electronics, was published in 1994, and he has written several additional textbooks. He now teaches digital electronics and related courses at Red River College in Winnipeg. Mr. Dueck is a member of the Association of Professional Engineers and Geoscientists of Manitoba (APEGM) and the Institute of Electrical and Electronics Engineers (IEEE). He served as chair of the Winnipeg Section of IEEE in 2002 and was branch counselor of the Red River College Student Branch from 1997-2006.