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Digital Design with RTL Design, VHDL, and Verilog 2nd edition [Kõva köide]

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(University of California, Riverside, USA)
  • Formaat: Hardback, 594 pages, kõrgus x laius x paksus: 236x193x25 mm, kaal: 1071 g
  • Ilmumisaeg: 26-Mar-2010
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 0470531088
  • ISBN-13: 9780470531082
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Digital Design with RTL Design, VHDL, and Verilog 2nd editionSuurem pilt
  • Formaat: Hardback, 594 pages, kõrgus x laius x paksus: 236x193x25 mm, kaal: 1071 g
  • Ilmumisaeg: 26-Mar-2010
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 0470531088
  • ISBN-13: 9780470531082
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780470531082.html
Märksõnad:

An eagerly anticipated, up-to-date guide to essential digital design fundamentals

Offering a modern, updated approach to digital design, this much-needed book reviews basic design fundamentals before diving into specific details of design optimization. You begin with an examination of the low-levels of design, noting a clear distinction between design and gate-level minimization. The author then progresses to the key uses of digital design today, and how it is used to build high-performance alternatives to software.

  • Offers a fresh, up-to-date approach to digital design, whereas most literature available is sorely outdated
  • Progresses though low levels of design, making a clear distinction between design and gate-level minimization
  • Addresses the various uses of digital design today
  • Enables you to gain a clearer understanding of applying digital design to your life

With this book by your side, you'll gain a better understanding of how to apply the material in the book to real-world scenarios.

Preface ix
To Students About To Study Digital Design ix
To Instructors of Digital Design ix
How to Use This Book xii
RTL-Focused Approach xii
Traditional Approach with Some Reordering xii
Traditional Approach xiii
Acknowledgements xiii
About the Cover xiv
About the Author xiv
Reviewers and Evaluators xv
CHAPTER 1 Introduction
1(34)
1.1 Digital Systems in the World Around Us
1(3)
1.2 The World of Digital Systems
4(18)
Digital versus Analog
4(5)
Digital Encodings and Binary Numbers---0s and 1s
9(13)
1.3 Implementing Digital Systems: Microprocessors versus Digital Circuits
22(6)
Software on Microprocessors: The Digital Workhorse
22(4)
Digital Design---When Microprocessors Aren't Good Enough
26(2)
1.4 About this Book
28(1)
1.5 Exercises
29(6)
CHAPTER 2 Combinational Logic Design
35(70)
2.1 Introduction
35(1)
2.2 Switches
36(4)
Electronics 101
36(1)
The Amazing Shrinking Switch
37(3)
2.3 The CMOS Transistor
40(3)
2.4 Boolean Logic Gates---Building Blocks for Digital Circuits
43(9)
Boolean Algebra and its Relation to Digital Circuits
43(3)
And, Or, & Not Gates
46(3)
Building Simple Circuits Using Gates
49(3)
2.5 Boolean Algebra
52(9)
Notation and Terminology
53(2)
Some Properties of Boolean Algebra
55(5)
Complementing a Function
60(1)
2.6 Representations of Boolean Functions
61(12)
Equations
62(1)
Circuits
62(1)
Truth Tables
62(2)
Converting among Boolean Function Representations
64(4)
Standard Representation and Canonical Form
68(3)
Multiple-Output Combinational Circuits
71(2)
2.7 Combinational Logic Design Process
73(7)
2.8 More Gates
80(4)
Nand & Nor
80(1)
Xor & Xnor
81(1)
Interesting Uses of these Additional Gates
82(1)
Completeness of Nand and of Nor
82(1)
Number of Possible Logic Gates
83(1)
2.9 Decoders and Muxes
84(7)
Decoders
84(2)
Multiplexers (Muxes)
86(5)
2.10 Additional Considerations
91(4)
Nonideal Gate Behavior---Delay
91(1)
Active Low Inputs
92(1)
Demultiplexers and Encoders
93(1)
Schematic Capture and Simulation
93(2)
2.11 Combinational Logic Optimizations and Tradeoffs (See Section 6.2)
95(1)
2.12 Combinational Logic Description Using Hardware Description Languages (See Section 9.2)
95(1)
2.13
Chapter Summary
96(1)
2.14 Exercises
96(9)
Chapter 3 Sequential Logic Design: Controllers
105(62)
3.1 Introduction
105(1)
3.2 Storing One Bit---Flip-Flops
106(16)
Feedback---The Basic Storage Method
106(1)
Basic SR Latch
107(4)
Level -Sensitive SR Latch
111(1)
Level-Sensitive D Latch---A Basic Bit Store
112(1)
Edge-Triggered D Flip-Flop---A Robust Bit Store
113(4)
Clocks and Synchronous Circuits
117(3)
Basic Register---Storing Multiple Bits
120(2)
3.3 Finite-State Machines (FSMs)
122(10)
Mathematical Formalism for Sequential Behavior---FSMs
124(5)
How to Capture Desired System Behavior as an FSM
129(3)
3.4 Controller Design
132(14)
Standard Controller Architecture for Implementing an FSM as a Sequential Circuit
132(1)
Controller (Sequential Logic) Design Process
133(7)
Converting a Circuit to an FSM (Reverse Engineering)
140(2)
Common Mistakes when Capturing FSMs
142(3)
FSM and Controller Conventions
145(1)
3.5 More on Flip-Flops and Controllers
146(7)
Non-Ideal Flip-Flop Behavior
146(3)
Flip-Flop Reset and Set Inputs
149(1)
Initial State of a Controller
150(1)
Non-Ideal Controller Behavior: Output Glitches
151(2)
3.6 Sequential Logic Optimizations and Tradeoffs (See Section 6.3)
153(1)
3.7 Sequential Logic Description Using Hardware Description Languages (See Section 9.3)
153(1)
3.8 Product Profile---Pacemaker
153(3)
3.9
Chapter Summary
156(1)
3.10 Exercises
157(10)
Chapter 4 Datapath Components
167(80)
4.1 Introduction
167(1)
4.2 Registers
168(13)
Parallel-Load Register
168(5)
Shift Register
173(2)
Multifunction Registers
175(4)
Register Design Process
179(2)
4.3 Adders
181(10)
Adder---Carry-Ripple Style
183(8)
4.4 Comparators
191(4)
Equality (Identity) Comparator
191(1)
Magnitude Comparator---Carry-Ripple Style
192(3)
4.5 Multiplier---Array-Style
195(1)
4.6 Subtractors and Signed Numbers
196(11)
Subtractor for Positive Numbers Only
196(4)
Representing Negative Numbers: Two's Complement Representation
200(3)
Building a Subtractor Using an Adder and Two's Complement
203(2)
Detecting Overflow
205(2)
4.7 Arithmetic-Logic Units---ALUs
207(3)
4.8 Shifters
210(5)
Simple Shifters
211(3)
Barrel Shifter
214(1)
4.9 Counters and Timers
215(10)
Up-Counter
216(1)
Up/Down-Counter
217(1)
Counter with Load
218(4)
Timers
222(3)
4.10 Register Files
225(5)
4.11 Datapath Component Tradeoffs (See Section 6.4)
230(1)
4.12 Datapath Component Description Using Hardware Description Languages (See Section 9.4)
230(1)
4.13 Product Profile: An Ultrasound Machine
230(7)
Functional Overview
231(3)
Digital Circuits in an Ultrasound Machine's Beamformer
234(3)
Future Challenges in Ultrasound
237(1)
4.14
Chapter Summary
237(1)
4.15 Exercises
238(9)
Chapter 5 Register-Transfer Level (RTL) Design
247(78)
5.1 Introduction
247(1)
5.2 High-Level State Machines
248(7)
5.3 RTL Design Process
255(9)
Step 2A---Creating a Datapath using Components from a Library
259(3)
Step 2B---Connecting the Datapath to a Controller
262(1)
Step 2C---Deriving the Controller's FSM
263(1)
5.4 More RTL Design
264(14)
Additional Datapath Components for the Library
264(1)
RTL Design Involving Register Files or Memories
265(6)
RTL Design Pitfall Involving Storage Updates
271(1)
RTL Design Involving a Timer
272(3)
A Data-Dominated RTL Design Example
275(3)
5.5 Determining Clock Frequency
278(3)
5.6 Behavioral-Level Design: C to Gates (Optional)
281(4)
5.7 Memory Components
285(14)
Random Access Memory (RAM)
286(2)
Bit Storage in a RAM
288(2)
Using a RAM
290(2)
Read-Only Memory (ROM)
292(2)
ROM Types
294(3)
Using a ROM
297(2)
The Blurring of the Distinction between RAM and ROM
299(1)
5.8 Queues (FIFOs)
299(4)
5.9 Multiple Processors
303(2)
5.10 Hierarchy---A Key Design Concept
305(4)
Managing Complexity
305(1)
Abstraction
306(1)
Composing a Larger Component from Smaller Versions of the Same Component
307(2)
5.11 RTL Design Optimizations and Tradeoffs (See Section 6.5)
309(1)
5.12 RTL Design Using Hardware Description Languages (See Section 9.5)
310(1)
5.13 Product Profile: Cell Phone
310(6)
Cells and Basestations
310(1)
How Cellular Phone Calls Work
311(1)
Inside a Cell Phone
312(4)
5.14
Chapter Summary
316(1)
5.15 Exercises
317(8)
Chapter 6 Optimizations and Tradeoffs
325(88)
6.1 Introduction
325(2)
6.2 Combinational Logic Optimizations and Tradeoffs
327(24)
Two-Level Size Optimization Using Algebraic Methods
327(2)
A Visual Method for Two-Level Size Optimization---K-Maps
329(7)
Don't Care Input Combinations
336(3)
Automating Two-Level Logic Size Optimization
339(9)
Multilevel Logic Optimization---Performance and Size Tradeoffs
348(3)
6.3 Sequential Logic Optimizations and Tradeoffs
351(14)
State Reduction
351(3)
State Encoding
354(6)
Moore versus Mealy FSMs
360(5)
6.4 Datapath Component Tradeoffs
365(12)
Faster Adders
365(10)
Smaller Multiplier---Sequential (Shift-and-Add) Style
375(2)
6.5 RTL Design Optimizations and Tradeoffs
377(9)
Pipelining
377(3)
Concurrency
380(1)
Component Allocation
381(1)
Operator Binding
382(1)
Operator Scheduling
383(3)
Moore versus Mealy High-Level State Machines
386(1)
6.6 More on Optimizations and Tradeoffs
386(7)
Serial versus Concurrent Computation
386(1)
Optimizations and Tradeoffs at Higher versus Lower Levels of Design
387(1)
Algorithm Selection
388(1)
Power Optimization
389(4)
6.7 Product Profile: Digital Video Player/Recorder
393(9)
Digital Video Overview
393(1)
DVD---One Form of Digital Video Storage
393(2)
MPEG-2 Video Encoding---Sending Frame Differences Using I-, P-, and B-Frames
395(1)
Transforming to the Frequency Domain for Further Compression
396(6)
6.8
Chapter Summary
402(1)
6.9 Exercises
403(10)
Chapter 7 Physical Implementation on ICs
413(48)
7.1 Introduction
413(1)
7.2 Manufactured IC Types
414(9)
Full-Custom Integrated Circuits
414(1)
Semicustom (Application-Specific) Integrated Circuits---ASICs
415(8)
7.3 Off-the-Shelf Programmable IC Type---FPGA
423(15)
Lookup Tables
424(2)
Mapping a Circuit among Multiple Lookup Tables
426(6)
Programmable Interconnects (Switch Matrices)
432(2)
Configurable Logic Block
434(2)
Overall FPGA Architecture
436(2)
7.4 Other Off-the-Shelf IC Types
438(8)
Off-the-Shelf Logic (SSI) IC
438(3)
Simple Programmable Logic Device (SPLD)
441(4)
Complex Programmable Logic Device (CPLD)
445(1)
FPGA-to-Structured-ASIC Flows
445(1)
7.5 IC Tradeoffs, Trends, and Comparisons
446(7)
Tradeoffs Among IC Types
447(1)
IC Technology Trend---Moore's Law
448(2)
Relative Popularity of IC Types
450(1)
ASSPs
450(1)
IC Types versus Processor Varieties
451(1)
FPGAs alongside Microprocessors
452(1)
7.6 Product Profile: Giant LED-Based Video Display with FPGAs
453(4)
7.7
Chapter Summary
457(1)
7.8 Exercises
457(4)
Chapter 8 Programmable Processors
461(26)
8.1 Introduction
461(1)
8.2 Basic Architecture
462(7)
Basic Datapath
462(3)
Basic Control Unit
465(4)
8.3 A Three-Instruction Programmable Processor
469(6)
A First Instruction Set with Three Instructions
469(2)
Control Unit and Datapath for the Three-Instruction Processor
471(4)
8.4 A Six-Instruction Programmable Processor
475(3)
Extending the Instruction Set
475(1)
Extending the Control Unit and Datapath
476(2)
8.5 Example Assembly and Machine Programs
478(2)
8.6 Further Extensions to the Programmable Processor
480(2)
Instruction Set Extensions
480(1)
Input/Output Extensions
481(1)
Performance Extensions
481(1)
8.7
Chapter Summary
482(1)
8.8 Exercises
483(4)
Chapter 9 Hardware Description Languages
487(50)
9.1 Introduction
487(2)
9.2 Combinational Logic Description Using Hardware Description Languages
489(12)
Structure
489(5)
Combinational Behavior
494(4)
Testbenches
498(3)
9.3 Sequential Logic Description Using Hardware Description Languages
501(8)
Register
501(2)
Oscillator
503(2)
Controllers
505(4)
9.4 Datapath Component Description Using Hardware Description Languages
509(8)
Full-Adders
509(2)
Carry-Ripple Adders
511(3)
Up-Counter
514(3)
9.5 RTL Design Using Hardware Description Languages
517(15)
High-Level State Machine of the Laser-Based Distance Measurer
517(6)
Controller and Datapath of the Laser-Based Distance Measurer
523(9)
9.6
Chapter Summary
532(1)
9.7 Exercises
532(5)
APPENDIX A Boolean Algebras
537(10)
A.1 Boolean Algebra
537(1)
A.2 Switching Algebra
538(2)
A.3 Important Theorems in Boolean Algebra
540(5)
A.4 Other Examples of Boolean Algebras
545(1)
A.5 Further Readings
545(2)
APPENDIX B Additional Topics in Binary Number Systems
547(10)
B.1 Introduction
547(1)
B.2 Real Number Representation
547(3)
B.3 Fixed Point Arithmetic
550(1)
B.4 Floating Point Representation
551(5)
The IEEE 754-1985 Standard
552(4)
B.5 Exercises
556(1)
APPENDIX C Extended RTL Design Example
557
C.1 Introduction
557(1)
C.2 Designing the Soda Dispenser Controller
558(4)
C.3 Understanding the Behavior of the Soda Dispenser Controller and Datapath
562
Frank Vahid is the author of Digital Design with RTL Design, VHDL, and Verilog, 2nd Edition, published by Wiley.