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Digital Electronic with VHDL [Multiple-component retail product]

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William Kleitz

Formaat: Multiple-component retail product, 960 pages, kõrgus x laius x paksus: 285x217x36 mm, kaal: 2245 g, Contains 1 Paperback / softback and 1 CD-ROM
Ilmumisaeg: 24-Jul-2003
Kirjastus: Pearson
ISBN-10: 0131100807
ISBN-13: 9780131100800

Teised raamatud teemal:

Electronics engineering - (Hetkel poes: 1 nimetust)

Multiple-component retail product
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Formaat: Multiple-component retail product, 960 pages, kõrgus x laius x paksus: 285x217x36 mm, kaal: 2245 g, Contains 1 Paperback / softback and 1 CD-ROM
Ilmumisaeg: 24-Jul-2003
Kirjastus: Pearson
ISBN-10: 0131100807
ISBN-13: 9780131100800

Teised raamatud teemal:

Electronics engineering - (Hetkel poes: 1 nimetust)

Püsilink: https://www.kriso.ee/db/9780131100800.html

Märksõnad:

For courses in Digital Electronics, and Digital Logic.

Digital Electronics with VHDL provides the fundamentals of digital circuitry, which are introduced using the fixed-function ICs and evolve into CPLDs (Complex Programming Logic Devices) programmed with VHDL (VHSIC Hardware Description Language). Basic logic gates are used to perform arithmetic operations; then the text proceeds through sequential logic and memory circuits to interface to modern PCs. This new textbook is designed to present practical examples; be easy to read, and to provide all of the information necessary for the motivated student to learn this new subject matter.

chapter 1 Number Systems and Codes

(26)

Outline

(1)

Objectives

(1)

Introduction

(1)

1-1 Digital Versus Analog

(1)

1-2 Digital Representations of Analog Quantities

(3)

1-3 Decimal Numbering System (Base 10)

(1)

1-4 Binary Numbering System (Base 2)

(2)

1-5 Decimal-to-Binary Conversion

(2)

1-6 Octal Numbering System (Base 8)

(1)

1-7 Octal Conversions

(2)

1-8 Hexadecimal Numbering System (Base 16)

(1)

1-9 Hexadecimal Conversions

(2)

1-10 Binary-Coded-Decimal System

(1)

1-11 Comparison of Numbering Systems

(1)

1-12 The ASCII Code

(2)

1-13 Applications of the Number Systems

(3)

Summary

(1)

Glossary

(1)

Problems

(1)

Schematic Interpretation Problems

(2)

Answers to Review Questions

(2)

chapter 2 Digital Electronic Signals and Switches

(30)

Outline

(1)

Objectives

(1)

Introduction

(1)

2-1 Digital Signals

(1)

2-2 Clock Waveform Timing

(2)

2-3 Serial Representation

(1)

2-4 Parallel Representation

(3)

2-5 Switches in Electronic Circuits

(1)

2-6 A Relay as a Switch

(3)

2-7 A Diode as a Switch

(3)

2-8 A Transistor as a Switch

(4)

2-9 The TTL Integrated Circuit

(3)

2-10 The CMOS Integrated Circuit

(1)

2-11 Surface-Mount Devices

(1)

Summary

(1)

Glossary

(1)

Problems

(3)

Schematic Interpretation Problems

(1)

Electronics Workbench®/MultiSIM® Exercises

(1)

Answers to Review Questions

(1)

chapter 3 Basic Logic Gates

(46)

Outline

(1)

Objectives

(1)

Introduction

(1)

3-1 The AND Gate

(2)

3-2 The OR Gate

(2)

3-3 Timing Analysis

(2)

3-4 Enable and Disable Functions

(2)

3-5 Using IC Logic Gates

(1)

3-6 Introduction to Troubleshooting Techniques

(5)

3-7 The Inverter

(1)

3-8 The NAND Gate

(2)

3-9 The NOR Gate

(2)

3-10 Logic Gate Waveform Generation

(6)

3-11 Using IC Logic Gates

(2)

3-12 Summary of the Basic Logic Gates and IEEE/IEC Standard Logic Symbols

(2)

Summary

(1)

Glossary

(1)

Problems

(10)

Schematic Interpretation Problems

100

(1)

Electronics Workbench®/MultiSIM® Exercises

101

(2)

Answers to Review Questions

103

(1)

chapter 4 Programmable Logic Devices: CPLDs and FPGAs with VHDL Design

104

(40)

Outline

104

(1)

Objectives

104

(1)

Introduction

104

(1)

4-1 PLD Design Flow

105

(2)

4-2 PLD Architecture

107

(5)

4-3 Using PLDs to Solve Basic Logic Designs

112

(6)

4-4 Tutorial for Using Altera's MAX+PLUS® II Design Software

118

(15)

4-5 CPLD Applications

133

(4)

Summary

137

(1)

Glossary

138

(1)

Problems

139

(1)

CPLD Problems

140

(4)

chapter 5 Boolean Algebra and Reduction Techniques

144

(78)

Outline

144

(1)

Objectives

144

(1)

Introduction

145

(1)

5-1 Combinational Logic

145

(4)

5-2 Boolean Algebra Laws and Rules

149

(5)

5-3 Simplification of Combinational Logic Circuits Using Boolean Algebra

154

(4)

5-4 Using MAX+PLUS II to Determine Simplified Equations

158

(5)

5-5 De Morgan's Theorem

163

(14)

5-6 Entering a Truth Table in VHDL Using a Vector Signal

177

(5)

5-7 The Universal Capability of NAND and NOR Gates

182

(5)

5-8 AND-OR-INVERT Gates for Implementing Sum-of-Products Expressions

187

(4)

5-9 Karnaugh Mapping

191

(6)

5-10 System Design Applications

197

(3)

Summary

200

(1)

Glossary

200

(2)

Problems

202

(12)

Schematic Interpretation Problems

214

(1)

Electronics Workbench®/MultiSIM® Exercises

214

(3)

CPLD Problems

217

(3)

Answers to Review Questions

220

(2)

chapter 6 Exclusive-OR and Exclusive-NOR Gates

222

(22)

Outline

222

(1)

Objectives

222

(1)

Introduction

222

(1)

6-1 The Exclusive-OR Gate

223

(1)

6-2 The Exclusive-NOR Gate

224

(3)

6-3 Parity Generator/Checker

227

(3)

6-4 System Design Applications

230

(2)

6-5 CPLD Design Applications with VHDL

232

(5)

Summary

237

(1)

Glossary

237

(1)

Problems

238

(3)

Schematic Interpretation Problems

241

(1)

Electronics Workbench®/MultiSIM® Exercises

241

(1)

CPLD Problems

242

(1)

Answers to Review Questions

243

(1)

chapter 7 Arithmetic Operations and Circuits

244

(48)

Outline

244

(1)

Objectives

244

(1)

Introduction

244

(1)

7-1 Binary Arithmetic

245

(6)

7-2 Two's-Complement Representation

251

(2)

7-3 Two's-Complement Arithmetic

253

(2)

7-4 Hexadecimal Arithmetic

255

(3)

7-5 BCD Arithmetic

258

(1)

7-6 Arithmetic Circuits

259

(5)

7-7 Four-Bit Full-Adder ICs

264

(3)

7-8 VHDL Adders Using Integer Arithmetic

267

(2)

7-9 System Design Applications

269

(3)

7-10 Arithmetic/Logic Units

272

(3)

7-11 CPLD Applications with VHDL and LPMs

275

(7)

Summary

282

(1)

Glossary

282

(2)

Problems

284

(4)

Schematic Interpretation Problems

288

(1)

Electronics Workbench®/MultiSIM ® Exercises

288

(1)

CPLD Problems

289

(1)

Answers to Review Questions

290

(2)

chapter 8 Code Converters, Multiplexers, and Demultiplexers

292

(68)

Outline

292

(1)

Objectives

292

(1)

Introduction

292

(1)

8-1 Comparators

293

(2)

8-2 VHDL Comparator Using IF-THEN-ELSE

295

(3)

8-3 Decoding

298

(8)

8-4 Decoders Implemented in the VHDL Language

306

(4)

8-5 Encoding

310

(6)

8-6 Code Converters

316

(7)

8-7 Multiplexers

323

(7)

8-8 Demultiplexers

330

(3)

8-9 System Design Applications

333

(8)

8-10 CPLD Design Applications Using LPMs

341

(3)

Summary

344

(1)

Glossary

345

(1)

Problems

346

(7)

Schematic Interpretation Problems

353

(1)

Electronics Workbench®/MultiSIM® Exercises

353

(3)

CPLD Problems

356

(2)

Answers to Review Questions

358

(2)

chapter 9 Logic Families and Their Characteristics

360

(44)

Outline

360

(1)

Objectives

360

(1)

Introduction

360

(1)

9-1 The TTL Family

361

(2)

9-2 TTL Voltage and Current Ratings

363

(9)

9-3 Other TTL Considerations

372

(5)

9-4 Improved TTL Series

377

(2)

9-5 The CMOS Family

379

(5)

9-6 Emitter-Coupled Logic

384

(2)

9-7 Comparing Logic Families

386

(1)

9-8 Interfacing Logic Families

387

(7)

9-9 CPLD Electrical Characteristics

394

(2)

Summary

396

(1)

Glossary

396

(2)

Problems

398

(3)

Schematic Interpretation Problems

401

(1)

Electronics Workbench®/MultiSIM® Exercises

402

(1)

CPLD Problems

402

(1)

Answers to Review Questions

403

(1)

chapter 10 Flip-Flops and Registers

404

(54)

Outline

404

(1)

Objectives

404

(1)

Introduction

404

(1)

10-1 S-R Flip-Flop

405

(4)

10-2 Gated S-R Flip-Flop

409

(1)

10-3 Gated D Flip-Flop

410

(1)

10-4 D Latch: 7475 IC; VHDL Description

411

(4)

10-5 D Flip-Flop: 7474 IC; VHDL Description

415

(9)

10-6 Master-Slave J-K Flip-Flop

424

(3)

10-7 Edge-Triggered J-K Flip-Flop with VHDL Model

427

(4)

10-8 Integrated-Circuit J-K Flip-Flop (7476, 74LS76)

431

(7)

10-9 Using an Octal D Flip-Flop in a Microcontroller Application

438

(2)

10-10 Using Altera's LPM Flip-Flop

440

(3)

Summary

443

(1)

Glossary

443

(2)

Problems

445

(7)

Schematic Interpretation Problems

452

(1)

Electronics Workbench®/MultiSIM® Exercises

452

(1)

CPLD Problems

453

(2)

Answers to Review Questions

455

(3)

chapter 11 Practical Considerations for Digital Design

458

(46)

Outline

458

(1)

Objectives

458

(1)

Introduction

458

(1)

11-1 Flip-Flop Time Parameters

459

(17)

11-2 Automatic Reset

476

(1)

11-3 Schmitt Trigger ICS

477

(5)

11-4 Switch Debouncing

482

(4)

11-5 Sizing Pull-Up Resistors

486

(1)

11-6 Practical Input and Output Considerations

487

(7)

Summary

494

(1)

Glossary

494

(3)

Problems

497

(5)

Schematic Interpretation Problems

502

(1)

Electronics Workbench®/MultiSIM® Exercises

502

(1)

Answers to Review Questions

503

(1)

chapter 12 Counter Circuits and VHDL State Machines

504

(88)

Outline

504

(1)

Objectives

504

(1)

Introduction

504

(2)

12-1 Analysis of Sequential Circuits

506

(3)

12-2 Ripple Counters: JK FFs and VHDL Description

509

(6)

12-3 Design of Divide-by-N Counters

515

(9)

12-4 Ripple Counter ICs

524

(6)

12-5 System Design Applications

530

(7)

12-6 Seven-Segment LED Display Decoders: The 7447 IC and VHDL Description

537

(8)

12-7 Synchronous Counters

545

(4)

12-8 Synchronous Up/Down-Counter ICs

549

(9)

12-9 Applications of Synchronous Counter ICs

558

(3)

12-10 VHDL and LPM Counters

561

(4)

12-11 Implementing State Machines in VHDL

565

(12)

Summary

577

(1)

Glossary

578

(2)

Problems

580

(5)

Schematic Interpretation Problems

585

(1)

Electronics Workbench®/MultiSIM® Exercises

586

(1)

CPLD Problems

587

(3)

Answers to Review Questions

590

(2)

chapter 13 Shift Registers

592

Outline

592

(1)

Objectives

592

(1)

Introduction

592

(1)

13-1 Shift Register Basics

593

(2)

13-2 Parallel-to-Serial Conversion

595

(1)

13-3 Recirculating Register

595

(2)

13-4 Serial-to-Parallel Conversion

597

(1)

13-5 Ring Shift Counter and Johnson Shift Counter

597

(3)

13-6 VHDL Description of Shift Registers

600

(1)

13-7 Shift Register ICs

601

(11)

13-8 System Design Applications for Shift Registers

612

(4)

13-9 Driving a Stepper Motor with a Shift Register

616

(4)

13-10 Three-State Buffers, Latches, and Transceivers

620

(3)

13-11 Using the LPM Shift Register and 74194 Macrofunction

623

(3)

13-12 Using VHDL Components and Instantiations

626

(4)

Summary

630

(1)

Glossary

631

(2)

Problems

633

(6)

Schematic Interpretation Problems

639

(1)

Electronics Workbench®/MultiSIM® Exercises

639

(1)

CPLD Problems

640

(3)

Answers to Review Questions

643

chapter 14 Multivibrators and the

555

(123)

Timer

644

(1)

Outline

644

(1)

Objectives

644

(1)

Introduction

644

(1)

14-1 Multivibrators

645

(1)

14-2 Capacitor Charge and Discharge Rates

645

(4)

14-3 Astable Multivibrators

649

(3)

14-4 Monostable Multivibrators

652

(2)

14-5 Integrated-Circuit Monostable Multivibrators

654

(4)

14-6 Retriggerable Monostable Multivibrators

658

(3)

14-7 Astable Operation of the 555 IC Timer

661

(5)

14-8 Monostable Operation of the 555 IC Timer

666

(3)

14-9 Crystal Oscillators

669

(2)

Summary

671

(1)

Glossary

671

(1)

Problems

672

(3)

Schematic Interpretation Problems

675

(1)

Electronics Workbench®/MultiSIM® Exercises

675

(1)

Answers to Review Questions

676

(2)

chapter 15 Interfacing to the Analog World

678

(36)

Outline

678

(1)

Objectives

678

(1)

Introduction

678

(1)

15-1 Digital and Analog Representations

679

(1)

15-2 Operational Amplifier Basics

680

(1)

15-3 Binary-Weighted DIA Converters

681

(1)

15-4 R/2R Ladder DIA Converters

682

(3)

15-5 Integrated-Circuit DIA Converters

685

(2)

15-6 Integrated-Circuit Data Converter Specifications

687

(2)

15-7 Parallel-Encoded A/D Converters

689

(1)

15-8 Counter-Ramp AID Converters

689

(2)

15-9 Successive-Approximation AID Conversion

691

(3)

15-10 Integrated-Circuit A/D Converters

694

(5)

15-11 Data Acquisition System Application

699

(3)

15-12 Transducers and Signal Conditioning

702

(4)

Summary

706

(1)

Glossary

707

(2)

Problems

709

(3)

Schematic Interpretation Problems

712

(1)

Electronics Workbench"/MultiSIM R Exercises

712

(1)

Answers to Review Questions

713

(1)

chapter 16 Semiconductor, Magnetic, and Optical Memory

714

(40)

Outline

714

(1)

Objectives

714

(1)

Introduction

714

(1)

16-1 Memory Concepts

715

(3)

16-2 Static RAMS

718

(7)

16-3 Dynamic RAMS

725

(6)

16-4 Read-Only Memories

731

(7)

16-5 Memory Expansion and Address Decoding Applications

738

(5)

16-6 Magnetic and Optical Storage

743

(4)

Summary

747

(1)

Glossary

748

(1)

Problems

749

(3)

Schematic Interpretation Problems

752

(1)

Electronics Workbench®/MultiSIM® Exercises

752

(1)

Answers to Review Questions

753

(1)

chapter 17 Microprocessor Fundamentals

754

(22)

Outline

754

(1)

Objectives

754

(1)

Introduction

754

(1)

17-1 Introduction to System Components and Buses

755

(3)

17-2 Software Control of Microprocessor Systems

758

(1)

17-3 Internal Architecture of a Microprocessor

759

(1)

17-4 Instruction Execution Within a Microprocessor

760

(3)

17-5 Hardware Requirements for Basic I/O Programming

763

(2)

17-6 Writing Assembly Language and Machine Language Programs

765

(3)

17-7 Survey of Microprocessors and Manufacturers

768

(1)

Summary of Instructions

769

(1)

Summary

769

(1)

Glossary

770

(1)

Problems

771

(2)

Schematic Interpretation Problems

773

(1)

Answers to Review Questions

774

(2)

chapter 18 The 8051 Microcontroller

776

(34)

Outline

776

(1)

Objectives

776

(1)

Introduction

777

(1)

18-1 The 8051 Family of Microcontrollers

777

(1)

18-2 8051 Architecture

777

(6)

18-3 Interfacing to External Memory

783

(2)

18-4 The 8051 Instruction Set

785

(6)

18-5 8051 Applications

791

(5)

18-6 Data Acquisition and Control System Application

796

(10)

Summary

806

(1)

Glossary

807

(1)

Problems

807

(2)

Schematic Interpretation Problems

809

(1)

Appendix A WWW Sites

810

(2)

Appendix B Manufacturers' Data Sheets

812

(59)

Appendix C Explanation of the IEEE/IEC Standard for Logic Symbols (Dependency Notation)

871

(5)

Appendix D Answers to Odd-Numbered Problems

876

(22)

Appendix E VHDL Language Reference

898

(7)

Appendix F Review of Basic Electricity Principles

905

(10)

Appendix G Schematic Diagrams for
Chapter-End Problems

915

(9)

Appendix H 8051 Instruction Set Summary

924

(5)

Index

929

(6)

Supplementary Index of ICs

935

Digital Electronic with VHDL [Multiple-component retail product]

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