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Digital Electronics 3: Finite-state Machines [Kõva köide]

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  • Formaat: Hardback, 336 pages, kõrgus x laius x paksus: 241x165x23 mm, kaal: 635 g
  • Ilmumisaeg: 11-Nov-2016
  • Kirjastus: ISTE Ltd and John Wiley & Sons Inc
  • ISBN-10: 1848219865
  • ISBN-13: 9781848219861
Teised raamatud teemal:
Digital Electronics 3: Finite-state MachinesSuurem pilt
  • Formaat: Hardback, 336 pages, kõrgus x laius x paksus: 241x165x23 mm, kaal: 635 g
  • Ilmumisaeg: 11-Nov-2016
  • Kirjastus: ISTE Ltd and John Wiley & Sons Inc
  • ISBN-10: 1848219865
  • ISBN-13: 9781848219861
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781848219861.html
Märksõnad:
This third volume in the comprehensive Digital Electronics series, which explores the basic principles and concepts of digital circuits, focuses on finite state machines. These machines are characterized by a behavior that is determined by a limited and defined number of states, the holding conditions for each state, and the branching conditions from one state to another. They only allow one transition at a time and can be divided into two components: a combinational logic circuit and a sequential logic circuit. The approach is gradual and relatively independent of each other chapters. To facilitate the assimilation and practical implementation of various concepts, the book is complemented by a selection of practical exercises.
Preface ix
Chapter 1 Synchronous Finite State Machines
1(168)
1.1 Introduction
1(1)
1.2 State diagram
2(4)
1.3 Design of synchronous finite state machines
6(1)
1.4 Examples
7(20)
1.4.1 Flip-flops
7(5)
1.4.2 Binary sequence detector
12(9)
1.4.3 State machine implementation based on a state table
21(1)
1.4.4 Variable width pulse generator
22(5)
1.5 Equivalent states and minimization of the number of states
27(28)
1.5.1 Implication table method
28(9)
1.5.2 Partitioning method
37(5)
1.5.3 Simplification of incompletely specified machines
42(13)
1.6 State encoding
55(6)
1.7 Transformation of Moore and Mealy state machines
61(2)
1.8 Splitting finite state machines
63(5)
1.8.1 Rules for splitting
63(1)
1.8.2 Example 1
64(3)
1.8.3 Example 2
67(1)
1.9 Sequence detector implementation based on a programmable circuit
68(2)
1.10 Practical considerations
70(9)
1.10.1 Propagation delays and race conditions
72(2)
1.10.2 Timing specifications
74(5)
1.11 Exercises
79(18)
1.12 Solutions
97(72)
Chapter 2 Algorithmic State Machines
169(44)
2.1 Introduction
169(1)
2.2 Structure of an ASM
169(1)
2.3 ASM chart
170(5)
2.4 Applications
175(25)
2.4.1 Serial adder/subtracter
175(8)
2.4.2 Multiplier based on addition and shift operations
183(4)
2.4.3 Divider based on subtraction and shift operations
187(2)
2.4.4 Controller for an automatic vending machine
189(4)
2.4.5 Traffic light controller
193(7)
2.5 Exercises
200(5)
2.6 Solutions
205(8)
Chapter 3 Asynchronous Finite State Machines
213(74)
3.1 Introduction
213(1)
3.2 Overview
214(1)
3.3 Gated D latch
214(4)
3.4 Muller C-element
218(2)
3.5 Self-timed circuit
220(4)
3.6 Encoding the states of an asynchronous state machine
224(3)
3.7 Synthesis of asynchronous circuits
227(13)
3.7.1 Oscillatory cycle
227(1)
3.7.2 Essential and d-trio hazards
228(11)
3.7.3 Design of asynchronous state machines
239(1)
3.8 Application examples of asynchronous state machines
240(7)
3.8.1 Pulse synchronizer
240(3)
3.8.2 Asynchronous counter
243(4)
3.9 Implementation of asynchronous machines using SR latches or C-elements
247(4)
3.10 Asynchronous state machine operating in pulse mode
251(5)
3.11 Asynchronous state machine operating in burst mode
256(2)
3.12 Exercises
258(8)
3.13 Solutions
266(21)
Appendix. Overview of VHDL Language
287(24)
A.1 Introduction
287(1)
A.2 Principles of VHDL
287(5)
A.2.1 Names
288(1)
A.2.2 Comments
288(1)
A.2.3 Library and packages
289(1)
A.2.4 Ports
289(1)
A.2.5 Signal and variable
289(1)
A.2.6 Data types and objects
289(1)
A.2.7 Attributes
290(1)
A.2.8 Entity and architecture
291(1)
A.3 Concurrent instructions
292(2)
A.3.1 Concurrent instructions with selective assignment
293(1)
A.3.2 Concurrent instructions with conditional assignment
293(1)
A.4 Components
294(4)
A.4.1 Generics
296(1)
A.4.2 The GENERATE Instruction
296(1)
A.4.3 Process
297(1)
A.5 Sequential structures
298(8)
A.5.1 The IF instruction
298(5)
A.5.2 CASE instruction
303(3)
A.6 Testbench
306(5)
Bibliography 311(2)
Index 313
Tertulien Ndjountche received a PhD degree in electrical engineering from Erlangen-Nuremberg University in Germany. He has worked as a professor and researcher at universities in Germany and Canada. He has published numerous technical papers and books in his fields of interest.