Preface |
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xix | |
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1 | (20) |
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1 | (3) |
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4 | (1) |
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5 | (1) |
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6 | (4) |
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Combinational Circuits versus Sequential Circuits |
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10 | (1) |
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10 | (1) |
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11 | (2) |
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Logic Values versus Physical Values |
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13 | (2) |
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Nonprogrammable, Programmable, and Hardware Programmable |
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15 | (1) |
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15 | (1) |
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DC, AC, and Transient Responses |
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16 | (2) |
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Programmable Logic Devices |
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18 | (1) |
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Circuit Synthesis and Simulation with VHDL |
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19 | (1) |
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Circuit Simulation with SPICE |
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19 | (1) |
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Gate-Level versus Transistor-Level Analysis |
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20 | (1) |
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21 | (26) |
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21 | (3) |
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Octal and Hexadecimal Codes |
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24 | (1) |
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24 | (1) |
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25 | (1) |
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Codes for Negative Numbers |
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26 | (4) |
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26 | (1) |
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26 | (1) |
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27 | (1) |
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28 | (2) |
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Floating-Point Representation |
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30 | (5) |
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30 | (3) |
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Floating-Point versus Integer |
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33 | (2) |
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35 | (1) |
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35 | (1) |
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36 | (1) |
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36 | (4) |
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36 | (1) |
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36 | (2) |
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38 | (1) |
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39 | (1) |
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40 | (7) |
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47 | (22) |
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47 | (2) |
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Signed Addition and Subtraction |
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49 | (3) |
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52 | (2) |
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54 | (2) |
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56 | (1) |
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57 | (1) |
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58 | (1) |
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Floating-Point Addition and Subtraction |
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59 | (2) |
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Floating-Point Multiplication |
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61 | (1) |
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62 | (1) |
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63 | (6) |
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Introduction to Digital Circuits |
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69 | (34) |
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Introduction to MOS Transistors |
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69 | (2) |
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71 | (6) |
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71 | (1) |
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72 | (1) |
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73 | (1) |
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74 | (1) |
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75 | (1) |
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Timing Diagrams for Combinational Circuits |
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75 | (2) |
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77 | (2) |
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79 | (2) |
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81 | (2) |
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83 | (1) |
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84 | (1) |
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85 | (1) |
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86 | (1) |
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87 | (2) |
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89 | (2) |
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91 | (2) |
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Pseudo-Random Sequence Generator |
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93 | (1) |
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94 | (9) |
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103 | (30) |
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103 | (5) |
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108 | (1) |
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Minterms and SOP Equations |
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108 | (2) |
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Maxterms and POS Equations |
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110 | (2) |
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Standard Circuits for SOP and POS Equations |
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112 | (5) |
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117 | (3) |
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120 | (1) |
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Other Function-Simplification Techniques |
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121 | (2) |
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The Quine-McCluskey Algorithm |
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121 | (2) |
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Other Simplification Algorithms |
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123 | (1) |
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Propagation Delay and Glitches |
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123 | (2) |
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125 | (8) |
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133 | (20) |
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133 | (2) |
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Parameters and Types of Line Codes |
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135 | (2) |
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137 | (1) |
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138 | (1) |
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139 | (1) |
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139 | (1) |
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140 | (1) |
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140 | (3) |
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143 | (5) |
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148 | (5) |
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Error-Detecting/Correcting Codes |
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153 | (28) |
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Codes for Error Detection and Error Correction |
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153 | (1) |
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Single Parity Check (SPC) Codes |
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154 | (1) |
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Cyclic Redundancy Check (CRC) Codes |
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155 | (1) |
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156 | (3) |
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159 | (2) |
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161 | (2) |
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163 | (4) |
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167 | (3) |
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170 | (1) |
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Low Density Parity Check (LDPC) Codes |
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171 | (3) |
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174 | (7) |
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181 | (16) |
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181 | (2) |
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The Bipolar Junction Transistor |
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183 | (1) |
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184 | (1) |
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185 | (4) |
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189 | (2) |
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191 | (1) |
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192 | (2) |
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192 | (1) |
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Heterojunction Bipolar Transistor |
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193 | (1) |
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194 | (3) |
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197 | (22) |
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197 | (1) |
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The Field-Effect Transistor (MOSFET) |
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198 | (3) |
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198 | (2) |
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200 | (1) |
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201 | (1) |
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202 | (3) |
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205 | (2) |
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207 | (2) |
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209 | (1) |
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210 | (2) |
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210 | (1) |
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211 | (1) |
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211 | (1) |
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212 | (7) |
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219 | (38) |
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219 | (1) |
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220 | (1) |
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Transistor-Transistor Logic (TTL) |
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221 | (4) |
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221 | (1) |
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222 | (1) |
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223 | (1) |
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224 | (1) |
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Supply Voltage, Signal Voltages, and Noise Margin |
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224 | (1) |
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225 | (1) |
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226 | (1) |
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227 | (3) |
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227 | (1) |
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227 | (1) |
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228 | (1) |
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229 | (1) |
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Supply Voltage, Signal Voltages, and Noise Margin |
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229 | (1) |
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229 | (1) |
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230 | (1) |
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230 | (1) |
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Other Static MOS Architectures |
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230 | (2) |
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230 | (1) |
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231 | (1) |
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232 | (1) |
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Dynamic MOS Architectures |
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232 | (3) |
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232 | (1) |
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233 | (1) |
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Clocked-CMOS (C2MOS) Logic |
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234 | (1) |
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235 | (13) |
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236 | (1) |
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CMOS and LVCMOS Standards |
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237 | (3) |
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240 | (4) |
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244 | (1) |
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244 | (2) |
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LVDS Example: PCI Express Bus |
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246 | (2) |
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248 | (9) |
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Combinational Logic Circuits |
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257 | (32) |
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Combinational versus Sequential Logic |
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257 | (1) |
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Logical versus Arithmetic Circuits |
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258 | (1) |
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258 | (1) |
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259 | (3) |
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260 | (1) |
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260 | (2) |
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262 | (6) |
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262 | (2) |
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Address Decoder with Enable |
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264 | (1) |
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264 | (1) |
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265 | (1) |
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266 | (2) |
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268 | (4) |
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269 | (1) |
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270 | (1) |
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271 | (1) |
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272 | (1) |
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272 | (2) |
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274 | (1) |
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275 | (2) |
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Nonoverlapping Clock Generators |
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277 | (1) |
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278 | (1) |
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279 | (1) |
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280 | (1) |
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281 | (6) |
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287 | (1) |
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287 | (2) |
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Combinational Arithmetic Circuits |
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289 | (30) |
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Arithmetic versus Logic Circuits |
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289 | (1) |
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290 | (3) |
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290 | (1) |
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291 | (2) |
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293 | (7) |
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Generate, Propagate, and Kill Signals |
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293 | (1) |
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Approaches for Fast Adders |
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294 | (1) |
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Manchester Carry-Chain Adder |
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295 | (1) |
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296 | (1) |
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297 | (1) |
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297 | (3) |
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300 | (1) |
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Signed Adders/Subtracters |
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301 | (2) |
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Signed versus Unsigned Adder? |
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301 | (1) |
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301 | (2) |
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Incrementer, Decrementer, and Two's Complementer |
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303 | (1) |
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303 | (1) |
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303 | (1) |
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303 | (1) |
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304 | (2) |
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306 | (1) |
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307 | (5) |
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Parallel Unsigned Multiplier |
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308 | (1) |
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Parallel Signed Multiplier |
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309 | (1) |
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Parallel-Serial Unsigned Multiplier |
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309 | (2) |
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ALU-Based Unsigned and Signed Multipliers |
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311 | (1) |
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312 | (1) |
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312 | (5) |
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317 | (1) |
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317 | (2) |
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319 | (34) |
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Sequential versus Combinational Logic |
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319 | (1) |
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320 | (1) |
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320 | (9) |
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320 | (2) |
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322 | (1) |
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323 | (1) |
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Static Multiplexer-Based DLs |
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324 | (2) |
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326 | (1) |
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327 | (1) |
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327 | (2) |
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329 | (3) |
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329 | (1) |
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330 | (1) |
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DFF Construction Approaches |
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331 | (1) |
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332 | (1) |
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Master-Slave D Flip-Flops |
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332 | (6) |
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Classical Master-Slave DFFs |
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332 | (2) |
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Clock Skew and Slow Clock Transitions |
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334 | (1) |
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Special Master-Slave DFFs |
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335 | (3) |
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338 | (4) |
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338 | (1) |
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339 | (3) |
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342 | (1) |
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Statistically Low-Power D Flip-Flops |
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343 | (1) |
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D Flip-Flop Control Ports |
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344 | (1) |
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DFF with Reset and Preset |
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344 | (1) |
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345 | (1) |
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345 | (1) |
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345 | (2) |
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347 | (5) |
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352 | (1) |
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353 | (44) |
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353 | (2) |
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355 | (13) |
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368 | (3) |
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371 | (3) |
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374 | (3) |
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377 | (4) |
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378 | (1) |
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379 | (2) |
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381 | (1) |
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Pseudo-Random Sequence Generators |
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381 | (2) |
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Scramblers and Descramblers |
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383 | (3) |
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Additive Scrambler-Descrambler |
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383 | (1) |
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Multiplicative Scrambler-Descrambler |
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384 | (2) |
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386 | (9) |
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395 | (1) |
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395 | (2) |
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397 | (36) |
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Finite State Machine Model |
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397 | (2) |
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Design of Finite State Machines |
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399 | (11) |
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System Resolution and Glitches |
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410 | (1) |
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Design of Large Finite State Machines |
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411 | (3) |
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Design of Finite State Machines with Complex Combinational Logic |
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414 | (3) |
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417 | (2) |
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Generic Signal Generator Design Technique |
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419 | (2) |
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Design of Symmetric-Phase Frequency Dividers |
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421 | (2) |
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Finite State Machine Encoding Styles |
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423 | (3) |
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426 | (6) |
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432 | (1) |
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433 | (18) |
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433 | (1) |
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Static Random Access Memory (SRAM) |
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434 | (4) |
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Dual and Quad Data Rate (DDR, QDR) SRAMs |
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438 | (1) |
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Dynamic Random Access Memory (DRAM) |
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439 | (3) |
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442 | (2) |
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Dual Data Rate (DDR, DDR2, DDR3) SDRAMs |
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444 | (2) |
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Content-Addressable Memory (CAM) for Cache Memories |
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446 | (1) |
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447 | (4) |
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451 | (16) |
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451 | (1) |
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Mask-Programmed ROM (MP-ROM) |
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452 | (1) |
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One-Time-Programmable ROM (OTP-ROM) |
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453 | (1) |
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Electrically Programmable ROM (EPROM) |
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453 | (2) |
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Electrically Erasable Programmable ROM (EEPROM) |
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455 | (1) |
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456 | (5) |
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Next-Generation Nonvolatile Memories |
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461 | (4) |
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462 | (1) |
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Magnetoresistive RAM (MRAM) |
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463 | (1) |
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464 | (1) |
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465 | (2) |
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Programmable Logic Devices |
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467 | (24) |
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The Concept of Programmable Logic Devices |
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467 | (1) |
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468 | (3) |
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468 | (2) |
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470 | (1) |
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471 | (1) |
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471 | (7) |
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471 | (4) |
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475 | (2) |
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477 | (1) |
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478 | (8) |
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478 | (1) |
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479 | (1) |
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480 | (1) |
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481 | (1) |
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481 | (1) |
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482 | (1) |
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483 | (2) |
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485 | (1) |
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485 | (1) |
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485 | (1) |
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486 | (5) |
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491 | (32) |
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492 | (1) |
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492 | (3) |
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Fundamental VHDL Packages |
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495 | (1) |
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496 | (2) |
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498 | (1) |
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498 | (2) |
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500 | (1) |
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Concurrent versus Sequential Code |
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501 | (1) |
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Concurrent Code (WHEN, GENERATE) |
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502 | (1) |
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Sequential Code (IF, CASE, LOOP, WAIT) |
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503 | (3) |
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Objects (CONSTANT, SIGNAL, VARIABLE) |
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506 | (3) |
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509 | (1) |
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510 | (3) |
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513 | (1) |
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514 | (2) |
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516 | (4) |
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520 | (3) |
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VHDL Design of Combinational Logic Circuits |
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523 | (16) |
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523 | (2) |
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BCD-to-SSD Conversion Function |
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525 | (2) |
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527 | (2) |
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529 | (1) |
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530 | (2) |
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Design of Synchronous RAM Memories |
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532 | (4) |
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536 | (3) |
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VHDL Design of Combinational Arithmetic Circuits |
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539 | (14) |
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539 | (1) |
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540 | (3) |
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Signed and Unsigned Adders/Subtracters |
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543 | (2) |
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Signed and Unsigned Multipliers/Dividers |
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545 | (2) |
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547 | (3) |
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550 | (3) |
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VHDL Design of Sequential Circuits |
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553 | (20) |
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553 | (3) |
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556 | (2) |
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558 | (3) |
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Fibonacci Series Generator |
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561 | (1) |
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562 | (3) |
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565 | (6) |
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571 | (2) |
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VHDL Design of State Machines |
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573 | (28) |
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573 | (2) |
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``Universal'' Signal Generator |
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575 | (3) |
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578 | (10) |
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588 | (9) |
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597 | (4) |
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Simulation with VHDL Testbenches |
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601 | (20) |
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Synthesis versus Simulation |
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601 | (1) |
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602 | (1) |
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603 | (2) |
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605 | (2) |
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607 | (1) |
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Writing Type I Testbenches |
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607 | (5) |
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Writing Type II Testbenches |
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612 | (3) |
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Writing Type III Testbenches |
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615 | (1) |
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Writing Type IV Testbenches |
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615 | (3) |
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618 | (3) |
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621 | (36) |
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621 | (1) |
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622 | (1) |
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Basic Structure of SPICE Code |
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623 | (2) |
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Declarations of Electronic Devices |
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625 | (5) |
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Declarations of Independent DC Sources |
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630 | (1) |
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Declarations of Independent AC Sources |
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631 | (4) |
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Declarations of Dependent Sources |
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635 | (1) |
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636 | (2) |
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638 | (3) |
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Transient Response Examples |
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641 | (3) |
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644 | (1) |
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645 | (3) |
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648 | (2) |
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Exercises Involving Combinational Logic Circuits |
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650 | (2) |
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Exercises Involving Combinational Arithmetic Circuits |
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652 | (2) |
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Exercises Involving Registers |
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654 | (1) |
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Exercises Involving Sequential Circuits |
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655 | (2) |
Appendix A ModelSim Tutorial |
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657 | (10) |
Appendix B PSpice Tutorial |
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667 | (6) |
References |
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673 | (6) |
Index |
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679 | |