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Digital Electronics and Design with VHDL [Kõva köide]

(Federal University of TechnologyParana, Curitiba, Brazil)
  • Formaat: Hardback, 720 pages, kõrgus x laius: 235x191 mm, kaal: 1420 g, Approx. 1020 illustrations; Illustrations, unspecified
  • Ilmumisaeg: 10-Mar-2008
  • Kirjastus: Morgan Kaufmann Publishers In
  • ISBN-10: 0123742706
  • ISBN-13: 9780123742704
  • Formaat: Hardback, 720 pages, kõrgus x laius: 235x191 mm, kaal: 1420 g, Approx. 1020 illustrations; Illustrations, unspecified
  • Ilmumisaeg: 10-Mar-2008
  • Kirjastus: Morgan Kaufmann Publishers In
  • ISBN-10: 0123742706
  • ISBN-13: 9780123742704
This book offers a friendly presentation of the fundamental principles and practices of modern digital design. Unlike any other book in this field, transistor-level implementations are also included, which allow the readers to gain a solid understanding of a circuit's real potential and limitations, and to develop a realistic perspective on the practical design of actual integrated circuits. Coverage includes the largest selection available of digital circuits in all categories (combinational, sequential, logical, or arithmetic). Coverage also includes detailed digital design techniques, with a thorough discussion on state-machine modeling for the analysis and design of complex sequential systems. Key technologies used in modern circuits are also described, including Bipolar, MOS, ROM/RAM, and CPLD/FPGA chips, as well as codes and techniques used in data storage and transmission. Designs are illustrated by means of complete, realistic applications using VHDL, where the complete code, comments and simulation results are included.

* Comprehensive coverage of fundamental digital concepts and principles, as well as complete, realistic, industry-standard designs
* Many circuits shown with internal details at the transistor-level, as in real integrated circuits
* Actual technologies used in state-of-the-art digital circuits presented in conjunction with fundamental concepts and principles
* Six chapters dedicated to VHDL-based techniques, with all VHDL-based designs synthesized onto CPLD/FPGA chips

Muu info

A "traditional" flow of topics, flexibly organized, applied to modern practice, superior pedagogy, at a student-friendly price!
Preface xix
Introduction
1(20)
Historical Notes
1(3)
Analog versus Digital
4(1)
Bits, Bytes, and Words
5(1)
Digital Circuits
6(4)
Combinational Circuits versus Sequential Circuits
10(1)
Integrated Circuits
10(1)
Printed Circuit Boards
11(2)
Logic Values versus Physical Values
13(2)
Nonprogrammable, Programmable, and Hardware Programmable
15(1)
Binary Waveforms
15(1)
DC, AC, and Transient Responses
16(2)
Programmable Logic Devices
18(1)
Circuit Synthesis and Simulation with VHDL
19(1)
Circuit Simulation with SPICE
19(1)
Gate-Level versus Transistor-Level Analysis
20(1)
Binary Representations
21(26)
Binary Code
21(3)
Octal and Hexadecimal Codes
24(1)
Gray Code
24(1)
BCD Code
25(1)
Codes for Negative Numbers
26(4)
Sign-Magnitude Code
26(1)
One's Complement Code
26(1)
Binary Addition
27(1)
Two's Complement Code
28(2)
Floating-Point Representation
30(5)
IEEE 754 Standard
30(3)
Floating-Point versus Integer
33(2)
ASCII Code
35(1)
ASCII Code
35(1)
Extended ASCII Code
36(1)
Unicode
36(4)
Unicode Characters
36(1)
UTF-8 Encoding
36(2)
UTF-16 Encoding
38(1)
UTF-32 Encoding
39(1)
Exercises
40(7)
Binary Arithmetic
47(22)
Unsigned Addition
47(2)
Signed Addition and Subtraction
49(3)
Shift Operations
52(2)
Unsigned Multiplication
54(2)
Signed Multiplication
56(1)
Unsigned Division
57(1)
Signed Division
58(1)
Floating-Point Addition and Subtraction
59(2)
Floating-Point Multiplication
61(1)
Floating-Point Division
62(1)
Exercises
63(6)
Introduction to Digital Circuits
69(34)
Introduction to MOS Transistors
69(2)
Inverter and CMOS Logic
71(6)
Inverter
71(1)
CMOS Logic
72(1)
Power Consumption
73(1)
Power-Delay Product
74(1)
Logic Voltages
75(1)
Timing Diagrams for Combinational Circuits
75(2)
AND and NAND Gates
77(2)
OR and NOR Gates
79(2)
XOR and XNOR Gates
81(2)
Modulo-2 Adder
83(1)
Buffer
84(1)
Tri-State Buffer
85(1)
Open-Drain Buffer
86(1)
D-Type Flip-Flop
87(2)
Shift Register
89(2)
Counters
91(2)
Pseudo-Random Sequence Generator
93(1)
Exercises
94(9)
Boolean Algebra
103(30)
Boolean Algebra
103(5)
Truth Tables
108(1)
Minterms and SOP Equations
108(2)
Maxterms and POS Equations
110(2)
Standard Circuits for SOP and POS Equations
112(5)
Karnaugh Maps
117(3)
Large Karnaugh Maps
120(1)
Other Function-Simplification Techniques
121(2)
The Quine-McCluskey Algorithm
121(2)
Other Simplification Algorithms
123(1)
Propagation Delay and Glitches
123(2)
Exercises
125(8)
Line Codes
133(20)
The Use of Line Codes
133(2)
Parameters and Types of Line Codes
135(2)
Unipolar Codes
137(1)
Polar Codes
138(1)
Bipolar Codes
139(1)
Biphase/Manchester Codes
139(1)
MLT Codes
140(1)
mB/nB Codes
140(3)
PAM Codes
143(5)
Exercises
148(5)
Error-Detecting/Correcting Codes
153(28)
Codes for Error Detection and Error Correction
153(1)
Single Parity Check (SPC) Codes
154(1)
Cyclic Redundancy Check (CRC) Codes
155(1)
Hamming Codes
156(3)
Reed-Solomon (RS) Codes
159(2)
Interleaving
161(2)
Convolutional Codes
163(4)
Viterbi Decoder
167(3)
Turbo Codes
170(1)
Low Density Parity Check (LDPC) Codes
171(3)
Exercises
174(7)
Bipolar Transistor
181(16)
Semiconductors
181(2)
The Bipolar Junction Transistor
183(1)
I-V Characteristics
184(1)
DC Response
185(4)
Transient Response
189(2)
AC Response
191(1)
Modern BJTs
192(2)
Polysilicon-Emitter BJT
192(1)
Heterojunction Bipolar Transistor
193(1)
Exercises
194(3)
MOS Transistor
197(22)
Semiconductors
197(1)
The Field-Effect Transistor (MOSFET)
198(3)
MOSFET Construction
198(2)
MOSFET Operation
200(1)
I-V Characteristics
201(1)
DC Response
202(3)
CMOS Inverter
205(2)
Transient Response
207(2)
AC Response
209(1)
Modern MOSFETs
210(2)
Strained Si-SiGe MOSFETs
210(1)
SOI MOSFETs
211(1)
BiCMOS Technologies
211(1)
Exercises
212(7)
Logic Families and I/Os
219(38)
BJT-Based Logic Families
219(1)
Diode-Transistor Logic
220(1)
Transistor-Transistor Logic (TTL)
221(4)
TTL Circuit
221(1)
Temperature Ranges
222(1)
TTL Versions
223(1)
Fan-In and Fan-Out
224(1)
Supply Voltage, Signal Voltages, and Noise Margin
224(1)
Emitter-Coupled Logic
225(1)
MOS-Based Logic Families
226(1)
CMOS Logic
227(3)
CMOS Circuits
227(1)
HC and HCT CMOS Families
227(1)
CMOS-TTL Interface
228(1)
Fan-In and Fan-Out
229(1)
Supply Voltage, Signal Voltages, and Noise Margin
229(1)
Low-Voltage CMOS
229(1)
Power Consumption
230(1)
Power-Delay Product
230(1)
Other Static MOS Architectures
230(2)
Pseudo-nMOS Logic
230(1)
Transmission-Gate Logic
231(1)
BiCMOS Logic
232(1)
Dynamic MOS Architectures
232(3)
Dynamic Logic
232(1)
Domino Logic
233(1)
Clocked-CMOS (C2MOS) Logic
234(1)
Modern I/O Standards
235(13)
TTL and LVTTL Standards
236(1)
CMOS and LVCMOS Standards
237(3)
SSTL Standards
240(4)
HSTL Standards
244(1)
LVDS Standard
244(2)
LVDS Example: PCI Express Bus
246(2)
Exercises
248(9)
Combinational Logic Circuits
257(32)
Combinational versus Sequential Logic
257(1)
Logical versus Arithmetic Circuits
258(1)
Fundamental Logic Gates
258(1)
Compound Gates
259(3)
SOP-Based CMOS Circuit
260(1)
POS-Based CMOS Circuit
260(2)
Encoders and Decoders
262(6)
Address Decoder
262(2)
Address Decoder with Enable
264(1)
Large Address Decoders
264(1)
Timing Diagrams
265(1)
Address Encoder
266(2)
Multiplexer
268(4)
Basic Multiplexers
269(1)
Large Multiplexers
270(1)
Timing Diagrams
271(1)
Parity Detector
272(1)
Priority Encoder
272(2)
Binary Sorter
274(1)
Shifters
275(2)
Nonoverlapping Clock Generators
277(1)
Short-Pulse Generators
278(1)
Schmitt Triggers
279(1)
Memories
280(1)
Exercises
281(6)
Exercises with VHDL
287(1)
Exercises with SPICE
287(2)
Combinational Arithmetic Circuits
289(30)
Arithmetic versus Logic Circuits
289(1)
Basic Adders
290(3)
Full-Adder Unit
290(1)
Carry-Ripple Adder
291(2)
Fast Adders
293(7)
Generate, Propagate, and Kill Signals
293(1)
Approaches for Fast Adders
294(1)
Manchester Carry-Chain Adder
295(1)
Carry-Skip Adder
296(1)
Carry-Select Adder
297(1)
Carry-Lookahead Adder
297(3)
Bit-Serial Adder
300(1)
Signed Adders/Subtracters
301(2)
Signed versus Unsigned Adder?
301(1)
Subtracters
301(2)
Incrementer, Decrementer, and Two's Complementer
303(1)
Incrementer
303(1)
Decrementer
303(1)
Two's Complementer
303(1)
Comparators
304(2)
Arithmetic-Logic Unit
306(1)
Multipliers
307(5)
Parallel Unsigned Multiplier
308(1)
Parallel Signed Multiplier
309(1)
Parallel-Serial Unsigned Multiplier
309(2)
ALU-Based Unsigned and Signed Multipliers
311(1)
Dividers
312(1)
Exercises
312(5)
Exercises with VHDL
317(1)
Exercises with SPICE
317(2)
Registers
319(34)
Sequential versus Combinational Logic
319(1)
SR Latch
320(1)
D Latch
320(9)
DL Operation
320(2)
Time-Related Parameters
322(1)
DL Circuits
323(1)
Static Multiplexer-Based DLs
324(2)
Static RAM-Type DLs
326(1)
Static Current-Mode DLs
327(1)
Dynamic DLs
327(2)
DFlip-Flop
329(3)
DFF Operation
329(1)
Time-Related Parameters
330(1)
DFF Construction Approaches
331(1)
DFF Circuits
332(1)
Master-Slave D Flip-Flops
332(6)
Classical Master-Slave DFFs
332(2)
Clock Skew and Slow Clock Transitions
334(1)
Special Master-Slave DFFs
335(3)
Pulse-Based D Flip-Flops
338(4)
Short-Pulse Generators
338(1)
Pulse-Based DFFs
339(3)
Dual-Edge D Flip-Flops
342(1)
Statistically Low-Power D Flip-Flops
343(1)
D Flip-Flop Control Ports
344(1)
DFF with Reset and Preset
344(1)
DFF with Enable
345(1)
DFF with Clear
345(1)
T Flip-Flop
345(2)
Exercises
347(5)
Exercises with SPICE
352(1)
Sequential Circuits
353(44)
Shift Registers
353(2)
Synchronous Counters
355(13)
Asynchronous Counters
368(3)
Signal Generators
371(3)
Frequency Dividers
374(3)
PLL and Prescalers
377(4)
Basic PLL
378(1)
Prescaler
379(2)
Programmable PLL
381(1)
Pseudo-Random Sequence Generators
381(2)
Scramblers and Descramblers
383(3)
Additive Scrambler-Descrambler
383(1)
Multiplicative Scrambler-Descrambler
384(2)
Exercises
386(9)
Exercises with VHDL
395(1)
Exercises with SPICE
395(2)
Finite State Machines
397(36)
Finite State Machine Model
397(2)
Design of Finite State Machines
399(11)
System Resolution and Glitches
410(1)
Design of Large Finite State Machines
411(3)
Design of Finite State Machines with Complex Combinational Logic
414(3)
Multi-Machine Designs
417(2)
Generic Signal Generator Design Technique
419(2)
Design of Symmetric-Phase Frequency Dividers
421(2)
Finite State Machine Encoding Styles
423(3)
Exercises
426(6)
Exercises with VHDL
432(1)
Volatile Memories
433(18)
Memory Types
433(1)
Static Random Access Memory (SRAM)
434(4)
Dual and Quad Data Rate (DDR, QDR) SRAMs
438(1)
Dynamic Random Access Memory (DRAM)
439(3)
Synchronous DRAM (SDRAM)
442(2)
Dual Data Rate (DDR, DDR2, DDR3) SDRAMs
444(2)
Content-Addressable Memory (CAM) for Cache Memories
446(1)
Exercises
447(4)
Nonvolatile Memories
451(16)
Memory Types
451(1)
Mask-Programmed ROM (MP-ROM)
452(1)
One-Time-Programmable ROM (OTP-ROM)
453(1)
Electrically Programmable ROM (EPROM)
453(2)
Electrically Erasable Programmable ROM (EEPROM)
455(1)
Flash Memory
456(5)
Next-Generation Nonvolatile Memories
461(4)
Ferroelectric RAM (FRAM)
462(1)
Magnetoresistive RAM (MRAM)
463(1)
Phase-Change RAM (PRAM)
464(1)
Exercises
465(2)
Programmable Logic Devices
467(24)
The Concept of Programmable Logic Devices
467(1)
SPLDs
468(3)
PAL Devices
468(2)
PLA Devices
470(1)
GAL Devices
471(1)
CPLDs
471(7)
Architecture
471(4)
Xilinx CPLDs
475(2)
Altera CPLDs
477(1)
FPGAs
478(8)
FPGA Technology
478(1)
FPGA Architecture
479(1)
Virtex CLB and Slice
480(1)
Stratix LAB and ALM
481(1)
RAM Blocks
481(1)
DSP Blocks
482(1)
Clock Management
483(2)
I/O Standards
485(1)
Additional Features
485(1)
Summary and Comparison
485(1)
Exercises
486(5)
VHDL Summary
491(32)
About VHDL
492(1)
Code Structure
492(3)
Fundamental VHDL Packages
495(1)
Predefined Data Types
496(2)
User Defined Data Types
498(1)
Operators
498(2)
Attributes
500(1)
Concurrent versus Sequential Code
501(1)
Concurrent Code (WHEN, GENERATE)
502(1)
Sequential Code (IF, CASE, LOOP, WAIT)
503(3)
Objects (CONSTANT, SIGNAL, VARIABLE)
506(3)
Packages
509(1)
Components
510(3)
Functions
513(1)
Procedures
514(2)
VHDL Template for FSMs
516(4)
Exercises
520(3)
VHDL Design of Combinational Logic Circuits
523(16)
Generic Address Decoder
523(2)
BCD-to-SSD Conversion Function
525(2)
Generic Multiplexer
527(2)
Generic Priority Encoder
529(1)
Design of ROM Memory
530(2)
Design of Synchronous RAM Memories
532(4)
Exercises
536(3)
VHDL Design of Combinational Arithmetic Circuits
539(14)
Carry-Ripple Adder
539(1)
Carry-Lookahead Adder
540(3)
Signed and Unsigned Adders/Subtracters
543(2)
Signed and Unsigned Multipliers/Dividers
545(2)
ALU
547(3)
Exercises
550(3)
VHDL Design of Sequential Circuits
553(20)
Shift Register with Load
553(3)
Switch Debouncer
556(2)
Timer
558(3)
Fibonacci Series Generator
561(1)
Frequency Meters
562(3)
Neural Networks
565(6)
Exercises
571(2)
VHDL Design of State Machines
573(28)
String Detector
573(2)
``Universal'' Signal Generator
575(3)
Car Alarm
578(10)
LCD Driver
588(9)
Exercises
597(4)
Simulation with VHDL Testbenches
601(20)
Synthesis versus Simulation
601(1)
Testbench Types
602(1)
Stimulus Generation
603(2)
Testing the Stimuli
605(2)
Testbench Template
607(1)
Writing Type I Testbenches
607(5)
Writing Type II Testbenches
612(3)
Writing Type III Testbenches
615(1)
Writing Type IV Testbenches
615(3)
Exercises
618(3)
Simulation with SPICE
621(36)
About SPICE
621(1)
Types of Analysis
622(1)
Basic Structure of SPICE Code
623(2)
Declarations of Electronic Devices
625(5)
Declarations of Independent DC Sources
630(1)
Declarations of Independent AC Sources
631(4)
Declarations of Dependent Sources
635(1)
SPICE Inputs and Outputs
636(2)
DC Response Examples
638(3)
Transient Response Examples
641(3)
AC Response Example
644(1)
Monte Carlo Analysis
645(3)
Subcircuits
648(2)
Exercises Involving Combinational Logic Circuits
650(2)
Exercises Involving Combinational Arithmetic Circuits
652(2)
Exercises Involving Registers
654(1)
Exercises Involving Sequential Circuits
655(2)
Appendix A ModelSim Tutorial 657(10)
Appendix B PSpice Tutorial 667(6)
References 673(6)
Index 679