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Digital Electronics with VHDL (Quartus II Version) [Kõva köide]

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  • Formaat: Hardback, 960 pages, kõrgus x laius x paksus: 284x214x41 mm, kaal: 2152 g
  • Ilmumisaeg: 23-May-2005
  • Kirjastus: Pearson
  • ISBN-10: 0131714902
  • ISBN-13: 9780131714908
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Digital Electronics with VHDL (Quartus II Version)Suurem pilt
  • Formaat: Hardback, 960 pages, kõrgus x laius x paksus: 284x214x41 mm, kaal: 2152 g
  • Ilmumisaeg: 23-May-2005
  • Kirjastus: Pearson
  • ISBN-10: 0131714902
  • ISBN-13: 9780131714908
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780131714908.html
Märksõnad:
For Digital Electronics courses requiring a comprehensive approach to Digital concepts with an emphasis on PLD programming and the integration of the latest Quartus II software.

 

This text presents a step-by-step, practical approach to an enhanced and easy understanding of digital circuitry fundamentals with coverage of CPLD's, VHDL and Altera's Quartus II software. Coverage begins with the basic logic gates used to perform arithmetic operations, and proceeds up through sequential logic and memory circuits used to interface to modern PCs. The author combines extensive teaching experience with practical examples in order to bring entry level students up to speed in this emerging field.
Number Systems and Codes
2(26)
Outline
2(1)
Objectives
2(1)
Introduction
3(1)
Digital Versus Analog
3(1)
Digital Representations of Analog Quantities
3(3)
Decimal Numbering System (Base 10)
6(1)
Binary Numbering System (Base 2)
7(2)
Decimal-to-Binary Conversion
9(2)
Octal Numbering System (Base 8)
11(1)
Octal Conversions
11(2)
Hexadecimal Numbering System (Base 16)
13(1)
Hexadecimal Conversions
14(2)
Binary-Coded-Decimal System
16(1)
Comparison of Numbering Systems
16(1)
The ASCII Code
16(2)
Applications of the Number Systems
18(10)
Summary
21(1)
Glossary
22(1)
Problems
23(1)
Schematic Interpretation Problems
24(1)
MultiSIM® Exercises
25(1)
Answers to Review Questions
26(2)
Digital Electronic Signals and Switches
28(30)
Outline
28(1)
Objectives
28(1)
Introduction
29(1)
Digital Signals
29(1)
Clock Waveform Timing
29(2)
Serial Representation
31(1)
Parallel Representation
32(3)
Switches in Electronic Circuits
35(1)
A Relay as a Switch
36(3)
A Diode as a Switch
39(3)
A Transistor as a Switch
42(4)
The TTL Integrated Circuit
46(3)
The CMOS Integrated Circuit
49(1)
Surface-Mount Devices
50(8)
Summary
51(1)
Glossary
52(1)
Problems
53(3)
Schematic Interpretation Problems
56(1)
MultiSIM® Exercises
56(1)
Answers to Review Questions
57(1)
Basic Logic Gates
58(46)
Outline
58(1)
Objectives
58(1)
Introduction
59(1)
The AND Gate
59(2)
The OR Gate
61(2)
Timing Analysis
63(2)
Enable and Disable Functions
65(2)
Using IC Logic Gates
67(1)
Introduction to Troubleshooting Techniques
68(5)
The Inverter
73(1)
The NAND Gate
74(2)
The NOR Gate
76(2)
Logic Gate Waveform Generation
78(6)
Using IC Logic Gates
84(2)
Summary of the Basic Logic Gates and IEEE/IEC Standard Logic Symbols
86(18)
Summary
88(1)
Glossary
89(1)
Problems
90(10)
Schematic Interpretation Problems
100(1)
MultiSIM® Exercises
101(2)
Answers to Review Questions
103(1)
Programmable Logic Devices: CPLDs and FPGAs with VHDL Design
104(52)
Outline
104(1)
Objectives
104(1)
Introduction
104(1)
PLD Design Flow
105(2)
PLD Architecture
107(5)
Using PLDs to Solve Basic Logic Designs
112(6)
Tutorial for Using Altera's Quartus® II Design and Simulation Software
118(27)
CPLD Applications
145(11)
Summary
149(1)
Glossary
150(1)
Problems
151(1)
CPLD Problems
152(4)
Boolean Algebra and Reduction Techniques
156(78)
Outline
156(1)
Objectives
156(1)
Introduction
157(1)
Combinational Logic
157(4)
Boolean Algebra Laws and Rules
161(5)
Simplification of Combinational Logic Circuits Using Boolean Algebra
166(4)
Using Quartus® II to Determine Simplified Equations
170(6)
De Morgan's Theorem
176(13)
Entering a Truth Table in VHDL Using a Vector Signal
189(5)
The Universal Capability of NAND and NOR Gates
194(5)
AND-OR-INVERT Gates for Implementing Sum-of-Products Expressions
199(4)
Karnaugh Mapping
203(6)
System Design Applications
209(25)
Summary
212(1)
Glossary
212(2)
Problems
214(12)
Schematic Interpretation Problems
226(1)
MultiSIM® Exercises
226(3)
CPLD Problems
229(3)
Answers to Review Questions
232(2)
Exclusive-OR and Exclusive-NOR Gates
234(22)
Outline
234(1)
Objectives
234(1)
Introduction
234(1)
The Exclusive-OR Gate
235(1)
The Exclusive-NOR Gate
236(3)
Parity Generator/Checker
239(3)
System Design Applications
242(2)
CPLD Design Applications with VHDL
244(12)
Summary
249(1)
Glossary
249(1)
Problems
250(3)
Schematic Interpretation Problems
253(1)
MultiSIM® Exercises
253(1)
CPLD Problems
254(1)
Answers to Review Questions
255(1)
Arithmetic Operations and Circuits
256(48)
Outline
256(1)
Objectives
256(1)
Introduction
256(1)
Binary Arithmetic
257(6)
Two's-Complement Representation
263(2)
Two's-Complement Arithmetic
265(2)
Hexadecimal Arithmetic
267(3)
BCD Arithmetic
270(1)
Arithmetic Circuits
271(5)
Four-Bit Full-Adder ICs
276(3)
VHDL Adders Using Integer Arithmetic
279(2)
System Design Applications
281(3)
Arithmetic/Logic Units
284(3)
CPLD Applications with VHDL and LPMs
287(17)
Summary
294(1)
Glossary
295(1)
Problems
296(4)
Schematic Interpretation Problems
300(1)
MultiSIM® Exercises
301(1)
CPLD Problems
301(2)
Answers to Review Questions
303(1)
Code Converters, Multiplexers, and Demultiplexers
304(68)
Outline
304(1)
Objectives
304(1)
Introduction
304(1)
Comparators
305(2)
VHDL Comparator Using If-Then-Else
307(3)
Decoding
310(8)
Decoders Implemented in the VHDL Language
318(4)
Encoding
322(6)
Code Converters
328(7)
Multiplexers
335(7)
Demultiplexers
342(3)
System Design Applications
345(8)
CPLD Design Applications Using LPMs
353(19)
Summary
357(1)
Glossary
357(1)
Problems
358(7)
Schematic Interpretation Problems
365(1)
MultiSIM® Exercises
365(3)
CPLD Problems
368(2)
Answers to Review Questions
370(2)
Logic Families and Their Characteristics
372(44)
Outline
372(1)
Objectives
372(1)
Introduction
372(1)
The TTL Family
373(2)
TTL Voltage and Current Ratings
375(9)
Other TTL Considerations
384(5)
Improved TTL Series
389(2)
The CMOS Family
391(5)
Emitter-Coupled Logic
396(2)
Comparing Logic Families
398(1)
Interfacing Logic Families
399(7)
CPLD Electrical Characteristics
406(10)
Summary
408(1)
Glossary
408(2)
Problems
410(3)
Schematic Interpretation Problems
413(1)
MultiSIM® Exercises
414(1)
CPLD Problems
414(1)
Answers to Review Questions
415(1)
Flip-Flops and Registers
416(54)
Outline
416(1)
Objectives
416(1)
Introduction
416(1)
S-R Flip-Flop
417(4)
Gated S-R Flip-Flop
421(1)
Gated D Flip-Flop
422(1)
D Latch: 7475 IC; VHDL Description
423(4)
D Flip-Flop; 7474 IC; VHDL Description
427(9)
Master--Slave J-K Flip-Flop
436(3)
Edge-Triggered J-K Flip-Flop with VHDL Model
439(4)
Integrated-Circuit J-K Flip-Flop (7476, 74LS76)
443(7)
Using an Octal D Flip-Flop in a Microcontroller Application
450(2)
Using Altera's LPM Flip-Flop
452(18)
Summary
455(1)
Glossary
455(2)
Problems
457(7)
Schematic Interpretation Problems
464(1)
MultiSIM® Exercises
464(1)
CPLD Problems
465(2)
Answers to Review Questions
467(3)
Practical Considerations for Digital Design
470(46)
Outline
470(1)
Objectives
470(1)
Introduction
470(1)
Flip-Flop Time Parameters
471(17)
Automatic Reset
488(1)
Schmitt Trigger ICs
489(5)
Switch Debouncing
494(4)
Sizing Pull-Up Resistors
498(1)
Practical Input and Output Considerations
499(17)
Summary
506(1)
Glossary
507(2)
Problems
509(5)
Schematic Interpretation Problems
514(1)
MultiSIM® Exercises
514(1)
Answers to Review Questions
515(1)
Counter Circuits and VHDL State Machines
516(88)
Outline
516(1)
Objectives
516(1)
Introduction
516(2)
Analysis of Sequential Circuits
518(3)
Ripple Counters: JK FFs and VHDL Description
521(6)
Design of Divide-by-N Counters
527(9)
Ripple Counter ICs
536(6)
System Design Applications
542(7)
Seven-Segment LED Display Decoders: The 7447 IC and VHDL Description
549(8)
Synchronous Counters
557(4)
Synchronous Up/Down-Counter ICs
561(9)
Applications of Synchronous Counter ICs
570(3)
VHDL and LPM Counters
573(4)
Implementing State Machines in VHDL
577(27)
Summary
589(1)
Glossary
590(2)
Problems
592(5)
Schematic Interpretation Problems
597(2)
MultiSIM® Exercises
599(1)
CPLD Problems
599(3)
Answers to Review Questions
602(2)
Shift Registers
604(52)
Outline
604(1)
Objectives
604(1)
Introduction
604(1)
Shift Register Basics
605(2)
Parallel-to-Serial Conversion
607(1)
Recirculating Register
607(2)
Serial-to-Parallel Conversion
609(1)
Ring Shift Counter and Johnson Shift Counter
609(3)
VHDL Description of Shift Registers
612(1)
Shift Register ICs
612(12)
System Design Applications for Shift Registers
624(4)
Driving a Stepper Motor with a Shift Register
628(4)
Three-State Buffers, Latches, and Transceivers
632(3)
Using the LPM Shift Register and 74194 Macrofunction
635(3)
Using VHDL Components and Instantiations
638(18)
Summary
642(1)
Glossary
643(1)
Problems
644(7)
Schematic Interpretation Problems
651(1)
MultiSIM® Exercises
651(1)
CPLD Problems
652(3)
Answers to Review Questions
655(1)
Multivibrators and the 555 Timer
656(34)
Outline
656(1)
Objectives
656(1)
Introduction
656(1)
Multivibrators
657(1)
Capacitor Charge and Discharge Rates
657(4)
Astable Multivibrators
661(3)
Monostable Multivibrators
664(2)
Integrated-Circuit Monostable Multivibrators
666(4)
Retriggerable Monostable Multivibrators
670(3)
Astable Operation of the 555 IC Timer
673(5)
Monostable Operation of the 555 IC Timer
678(3)
Crystal Oscillators
681(9)
Summary
683(1)
Glossary
683(1)
Problems
684(3)
Schematic Interpretation Problems
687(1)
MultiSIM® Exercises
687(1)
Answers to Review Questions
688(2)
Interfacing to the Analog World
690(36)
Outline
690(1)
Objectives
690(1)
Introduction
690(1)
Digital and Analog Representations
691(1)
Operational Amplifier Basics
692(1)
Binary-Weighted D/A Converters
693(1)
R/2R Ladder D/A Converters
694(3)
Integrated-Circuit D/A Converters
697(2)
Integrated-Circuit Data Converter Specifications
699(2)
Parallel-Encoded A/D Converters
701(1)
Counter-Ramp A/D Converters
701(2)
Successive-Approximation A/D Conversion
703(3)
Integrated-Circuit A/D Converters
706(5)
Data Acquisition System Application
711(3)
Transducers and Signal Conditioning
714(12)
Summary
718(1)
Glossary
719(1)
Problems
720(4)
Schematic Interpretation Problems
724(1)
MultiSIM® Exercises
724(1)
Answers to Review Questions
725(1)
Semiconductor, Magnetic, and Optical Memory
726(40)
Outline
726(1)
Objectives
726(1)
Introduction
726(1)
Memory Concepts
727(3)
Static RAMs
730(7)
Dynamic RAMs
737(6)
Read-Only Memories
743(7)
Memory Expansion and Address Decoding Applications
750(5)
Magnetic and Optical Storage
755(11)
Summary
759(1)
Glossary
760(1)
Problems
761(3)
Schematic Interpretation Problems
764(1)
MultiSIM® Exercises
764(1)
Answers to Review Questions
765(1)
Microprocessor Fundamentals
766(22)
Outline
766(1)
Objectives
766(1)
Introduction
766(1)
Introduction to System Components and Buses
767(3)
Software Control of Microprocessor Systems
770(1)
Internal Architecture of a Microprocessor
771(1)
Instruction Execution within a Microprocessor
772(3)
Hardware Requirements for Basic I/O Programming
775(2)
Writing Assembly Language and Machine Language Programs
777(3)
Survey of Microprocessors and Manufacturers
780(8)
Summary of Instructions
781(1)
Summary
781(1)
Glossary
782(1)
Problems
783(2)
Schematic Interpretation Problems
785(1)
Answers to Review Questions
786(2)
The 8051 Microcontroller
788(34)
Outline
788(1)
Objectives
788(1)
Introduction
789(1)
The 8051 Family of Microcontrollers
789(1)
8051 Architecture
789(6)
Interfacing to External Memory
795(2)
The 8051 Instruction Set
797(6)
8051 Applications
803(4)
Data Acquisition and Control System Application
807(15)
Summary
818(1)
Glossary
818(1)
Problems
819(2)
Schematic Interpretation Problems
821(1)
Appendix A WWW Sites 822(2)
Appendix B Manufacturers' Data Sheets 824(52)
Appendix C Explanation of the IEEE/IEC Standard for Logic Symbols (Dependency Notation) 876(4)
Appendix D Answers to Odd-Numbered Problems 880(22)
Appendix E VHDL Language Reference 902(6)
Appendix F Review of Basic Electricity Principles 908(11)
Appendix G Schematic Diagrams for
Chapter-End Problems		 919(9)
Appendix H 8051 Instruction Set Summary 928(6)
Index 934(4)
Supplementary Index of ICs 938