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Digital Logic and Microprocessor Design with Interfacing 2nd edition [Kõva köide]

  • Formaat: Hardback, 608 pages, kõrgus x laius x paksus: 234x188x30 mm, kaal: 1089 g, Illustrations, unspecified
  • Ilmumisaeg: 01-Jan-2017
  • Kirjastus: CENGAGE Learning Custom Publishing
  • ISBN-10: 1305859456
  • ISBN-13: 9781305859456
Teised raamatud teemal:
Digital Logic and Microprocessor Design with Interfacing 2nd editionSuurem pilt
  • Formaat: Hardback, 608 pages, kõrgus x laius x paksus: 234x188x30 mm, kaal: 1089 g, Illustrations, unspecified
  • Ilmumisaeg: 01-Jan-2017
  • Kirjastus: CENGAGE Learning Custom Publishing
  • ISBN-10: 1305859456
  • ISBN-13: 9781305859456
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781305859456.html
Märksõnad:
Learn how to design digital logic circuits, specifically combinational and sequential circuits, with DIGITAL LOGIC AND MICROPROCESSOR DESIGN WITH INTERFACING, 2E. This book teaches you how to put these two types of circuits together to form both dedicated and general-purpose microprocessors. This book's unique approach combines the use of logic principles with the building of individual components to create data paths and control units. With this book you are able to design simple microprocessors, implement them in real hardware, and interface them to real-world devices. Watch the exciting process as your own microprocessor comes to life in real hardware using the knowledge and skills you gain from DIGITAL LOGIC AND MICROPROCESSOR DESIGN WITH INTERFACING, 2E.
Preface xv
About the Author xxi
Chapter 1 Introduction to Microprocessor Design 1(17)
1.1 Overview of Microprocessor Design
3(3)
1.2 Design Abstraction Levels
6(1)
1.3 Examples of a 2-to-1 Multiplexer
7(4)
1.3.1 Behavioral Level
7(2)
1.3.2 Gate Level
9(2)
1.3.3 Transistor Level
11(1)
1.4 Introduction to Hardware Description Language
11(4)
1.5 Synthesis
15(1)
1.6 Going Forward
16(1)
1.7 Problems
17(1)
Chapter 2 Fundamentals of Digital Circuits 18(47)
2.1 Binary Numbers
19(8)
2.1.1 Counting in Binary
20(1)
2.1.2 Converting between Binary and Decimal
20(3)
2.1.3 Octal and Hexadecimal Notations
23(2)
2.1.4 Binary Number Arithmetic
25(2)
2.2 Negative Numbers
27(5)
2.2.1 Two's Complement Representation
27(2)
2.2.2 Sign Extension
29(1)
2.2.3 Signed Number Arithmetic
30(2)
2.3 Binary Switch
32(1)
2.4 Basic Logic Operators and Logic Expressions
33(2)
2.5 Logic Gates
35(1)
2.6 Truth Tables
36(2)
2.7 Boolean Algebra and Boolean Equations
38(8)
2.7.1 Boolean Algebra
38(3)
2.7.2 Duality Principle
41(1)
2.7.3 Boolean Functions and Their Inverses
41(5)
2.8 Minterms and Maxterms
46(6)
2.8.1 Minterms
46(3)
2.8.2 Maxterms
49(3)
2.9 Canonical, Standard, and Non-Standard Forms
52(1)
2.10 Digital Circuits
53(1)
2.11 Designing a Car Security System
54(3)
2.12 Verilog and VHDL Code for Digital Circuits
57(2)
2.12.1 Verilog Code for a Boolean Function
57(1)
2.12.2 VHDL Code for a Boolean Function
58(1)
2.13 Problems
59(6)
Chapter 3 Combinational Circuits 65(47)
3.1 Analysis of Combinational Circuits
66(6)
3.1.1 Using a Truth Table
67(3)
3.1.2 Using a Boolean Function
70(2)
3.2 Synthesis of Combinational Circuits
72(4)
3.2.1 Using Only NAND Gates
75(1)
3.3 Minimization of Combinational Circuits
76(13)
3.3.1 Boolean Algebra
77(1)
3.3.2 Karnaugh Maps
78(7)
3.3.3 Don't-Cares
85(1)
3.3.4 Tabulation Method
86(3)
3.4 Timing Hazards and Glitches
89(3)
3.4.1 Using Glitches
91(1)
3.5 BCD to 7-Segment Decoder
92(3)
3.6 Verilog and VHDL Code for Combinational Circuits
95(11)
3.6.1 Structural Verilog Code
95(2)
3.6.2 Structural VHDL Code
97(4)
3.6.3 Dataflow Verilog Code
101(1)
3.6.4 Dataflow VHDL Code
102(1)
3.6.5 Behavioral Verilog Code
103(1)
3.6.6 Behavioral VHDL Code
104(2)
3.7 Problems
106(6)
Chapter 4 Standard Combinational Components 112(45)
4.1 Signal Naming Conventions
113(1)
4.2 Multiplexer
114(3)
4.3 Adder
117(6)
4.3.1 Full Adder
117(1)
4.3.2 Ripple-Carry Adder
118(2)
4.3.3 Carry-Lookahead Adder
120(3)
4.4 Subtractor
123(2)
4.5 Adder-Subtractor Combination
125(4)
4.6 Arithmetic Logic Unit
129(8)
4.7 Decoder
137(3)
4.8 Tri-State Buffer
140(2)
4.9 Comparator
142(4)
4.10 Shifter
146(3)
4.11 Multiplier
149(2)
4.12 Problems
151(6)
Chapter 5 Sequential Circuits 157(58)
5.1 Bistable Element
159(1)
5.2 SR Latch
160(3)
5.3 Car Security System-Version 2
163(1)
5.4 SR Latch with Enable
164(1)
5.5 D Latch
164(2)
5.6 D Latch with Enable
166(1)
5.7 Verilog and VHDL Code for Memory Elements
166(3)
5.7.1 VHDL Code for a D Latch with Enable
168(1)
5.7.2 Verilog Code for a D Latch with Enable
169(1)
5.8 Clock
169(2)
5.9 D Flip-Flop
171(5)
5.9.1 Alternative Smaller Circuit
175(1)
5.10 D Flip-Flop with Enable
176(4)
5.10.1 Asynchronous Inputs
177(3)
5.11 Description of a Flip-Flop
180(1)
5.11.1 Characteristic Table
180(1)
5.11.2 Characteristic Equation
180(1)
5.11.3 State Diagram
180(1)
5.12 Register
181(1)
5.13 Register File
182(6)
5.14 Memories
188(9)
5.14.1 ROM
190(2)
5.14.2 RAM
192(5)
5.15 Shift Registers
197(8)
5.15.1 Serial-to-Parallel Shift Register
199(1)
5.15.2 Serial-to-Parallel and Parallel-to-Serial Shift Register
200(2)
5.15.3 Linear Feedback Shift Register
202(3)
5.16 Counters
205(5)
5.16.1 Binary Up Counter
205(2)
5.16.2 Binary Up Counter with Parallel Load
207(3)
5.17 Timing Issues
210(1)
5.18 Problems
211(4)
Chapter 6 Finite-State Machines 215(68)
6.1 Finite-State Machine Models
217(4)
6.2 State Diagrams
221(3)
6.3 Analysis of Finite-State Machines
224(10)
6.3.1 Next-State Equations
225(1)
6.3.2 Next-State Table
226(2)
6.3.3 Output Equations
228(1)
6.3.4 Output Table
228(1)
6.3.5 State Diagram
229(1)
6.3.6 Example
230(4)
6.4 Synthesis of Finite-State Machines
234(5)
6.4.1 State Diagram
235(1)
6.4.2 Next-State Table
236(1)
6.4.3 Next-State Equations
237(1)
6.4.4 Output Table and Output Equations
237(1)
6.4.5 FSM Circuit
238(1)
6.5 Optimizations for FSMs
239(4)
6.5.1 State Reduction
239(1)
6.5.2 State Encoding
240(3)
6.5.3 Unused States
243(1)
6.6 FSM Construction Examples
243(18)
6.6.1 Car Security System-Version 3
243(2)
6.6.2 Modulo-6 Up-Counter
245(4)
6.6.3 One-Shot Circuit
249(2)
6.6.4 Simple Microprocessor Control Unit
251(3)
6.6.5 Elevator Controller Using a Moore FSM
254(4)
6.6.6 Elevator Controller Using a Mealy FSM
258(3)
6.7 Verilog and VHDL Code for FSM Circuits
261(9)
6.7.1 Behavioral Verilog Code for a Moore FSM
261(4)
6.7.2 Behavioral Verilog Code for a Mealy FSM
265(1)
6.7.3 Behavioral VHDL Code for a Moore FSM
266(3)
6.7.4 Behavioral VHDL Code for a Mealy FSM
269(1)
6.8 Problems
270(13)
Chapter 7 Dedicated Microprocessors 283(80)
7.1 Need for a Datapath
286(1)
7.2 Constructing the Datapath
287(15)
7.2.1 Selecting Registers
293(1)
7.2.2 Selecting Functional Units
294(1)
7.2.3 Data Transfer Methods
295(2)
7.2.4 Generating Status Signals
297(5)
7.3 Constructing the Control Unit
302(18)
7.3.1 Deriving the Control Signals
303(2)
7.3.2 Deriving the State Diagram
305(7)
7.3.3 Timing Issues
312(3)
7.3.4 Deriving the FSM Circuit
315(5)
7.4 Constructing the Complete Microprocessor
320(3)
7.5 Dedicated Microprocessor Construction Examples
323(18)
7.5.1 Greatest Common Divisor
323(7)
7.5.2 High-Low Number Guessing Game
330(7)
7.5.3 Traffic Light Controller
337(4)
7.6 Verilog and VHDL Code for Dedicated Microprocessors
341(15)
7.6.1 FSM+D Model
342(9)
7.6.2 FSMD Model
351(3)
7.6.3 Algorithmic Model
354(2)
7.7 Problems
356(7)
Chapter 8 General-Purpose Microprocessors 363(52)
8.1 Overview of the CPU Design
364(2)
8.2 The EC-1 General-Purpose Microprocessor
366(10)
8.2.1 Instruction Set
366(1)
8.2.2 Datapath
367(2)
8.2.3 Control Unit
369(4)
8.2.4 Complete Circuit
373(1)
8.2.5 Sample Program
373(2)
8.2.6 Simulation
375(1)
8.2.7 Hardware Implementation
375(1)
8.3 The EC-2 General-Purpose Microprocessor
376(12)
8.3.1 Instruction Set
376(1)
8.3.2 Datapath
377(2)
8.3.3 Control Unit
379(5)
8.3.4 Complete Circuit
384(1)
8.3.5 Sample Program
384(3)
8.3.6 Hardware Implementation
387(1)
8.4 Extending the EC-2 Instruction Set
388(3)
8.5 Using and Interfacing the EC-2
391(4)
8.6 Pipelining
395(4)
8.6.1 Basic Pipelined Processor
395(2)
8.6.2 Pipeline Hazards
397(2)
8.7 Verilog and VHDL Code for General-Purpose Microprocessors
399(12)
8.7.1 FSM+D Model
399(6)
8.7.2 FSMD Model
405(6)
8.8 Problems
411(4)
Chapter 9 Interfacing Microprocessors 415(71)
9.1 Multiplexing 7-Segment LED Display
416(4)
9.1.1 Theory of Operation
416(1)
9.1.2 Controller Design
417(3)
9.2 Issues with Interfacing Switches
420(7)
9.3 3 x 4 Keypad Controller
427(4)
9.3.1 Theory of Operation
427(2)
9.3.2 Controller Design
429(2)
9.4 PS2 Keyboard and Mouse
431(13)
9.4.1 Theory of Operation-PS2 Keyboard
431(1)
9.4.2 Controller Design-PS2 Keyboard
432(4)
9.4.3 Theory of Operation-PS2 Mouse
436(2)
9.4.4 Controller Design-PS2 Mouse
438(6)
9.5 RS-232 Controller for Bluetooth Communication
444(6)
9.5.1 Theory of Operation-RS-232
445(1)
9.5.2 Controller Design-RS-232
446(3)
9.5.3 Implementation
449(1)
9.6 Liquid-Crystal Display Controller
450(7)
9.6.1 Theory of Operation
450(2)
9.6.2 Controller Design
452(5)
9.7 VGA Monitor Controller
457(10)
9.7.1 Theory of Operation
457(3)
9.7.2 Controller Design
460(6)
9.7.3 Implementation
466(1)
9.8 A/D Controller for Temperature Sensor
467(8)
9.8.1 Theory of Operation
467(2)
9.8.2 Controller Design
469(5)
9.8.3 Implementation
474(1)
9.9 I2C Bus Controller for Real-Time Clock
475(9)
9.9.1 Theory of Operation
475(3)
9.9.2 Controller Design
478(5)
9.9.3 Implementation
483(1)
9.10 Problems
484(2)
Appendix A Xilinx Development Tutorial 486(26)
A.1 Starting ISE
486(6)
A.1.1 Creating a New Project
486(3)
A.1.2 Specifying the FPGA
489(3)
A.2 Creating a New Schematic Source File
492(8)
A.2.1 Drawing Your Schematic Circuit
493(2)
A.2.2 Creating and Using a Schematic Symbol
495(2)
A.2.3 Editing a Schematic Symbol
497(3)
A.2.4 Using a Schematic Symbol in Another Project
500(1)
A.3 Creating a New Verilog or VHDL Source File
500(1)
A.4 Setting the Top-Level Module Design File
500(1)
A.5 Mapping the I/O Signals
500(3)
A.5.1 Using PlanAhead for Mapping the Pins
501(2)
A.5.2 Faster Alternative Method for Mapping the Pins
503(1)
A.6 Synthesis and Implementation
503(2)
A.7 Programming the Circuit to the FPGA
505(4)
A.8 Problems
509(3)
Appendix B Altera Development Tutorial 512(21)
B.1 Starting Quartus
512(4)
B.1.1 Creating a New Project
512(2)
B.1.2 Specifying the FPGA
514(2)
B.2 Using the Graphic Editor
516(5)
B.2.1 Starting the Graphic Editor
516(1)
B.2.2 Drawing Tools
516(1)
B.2.3 Inserting Logic Symbols
517(1)
B.2.4 Selecting, Moving, Copying, and Deleting Logic Symbols
518(1)
B.2.5 Making and Naming Connections
519(2)
B.2.6 Selecting, Moving, and Deleting Connection Lines
521(1)
B.3 Managing Files in a Project
521(2)
B.3.1 Design Files in a Project
522(1)
B.3.2 Creating a New Verilog or VHDL Source File
522(1)
B.3.3 Opening a Design File
522(1)
B.3.4 Adding Design Files to a Project
523(1)
B.3.5 Deleting Design Files from a Project
523(1)
B.3.6 Setting the Top-Level Entity Design File
523(1)
B.3.7 Saving the Project
523(1)
B.4 Analysis and Synthesis
523(1)
B.5 Creating and Using a Logic Symbol
524(1)
B.6 Mapping the I/O Signals
525(2)
B.6.1 Faster Alternative Method for Mapping the Pins
527(1)
B.7 Fitting the Netlist and Pins to the FPGA
527(1)
B.8 Programming the Circuit to the FPGA
528(1)
B.9 Problems
529(4)
Appendix C Verilog Summary 533(20)
C.1 Basic Language Elements
533(7)
C.1.1 Keywords
533(1)
C.1.2 Comments
534(1)
C.1.3 Identifiers
534(1)
C.1.4 Signals
534(1)
C.1.5 Numbers and Strings
534(1)
C.1.6 Constants
535(1)
C.1.7 Data Types
536(1)
C.1.8 Data Operators
536(1)
C.1.9 Module
537(2)
C.1.10 Module Parameter
539(1)
C.2 Behavioral Model
540(8)
C.2.1 Assignment
540(1)
C.2.2 initial
541(1)
C.2.3 always
542(1)
C.2.4 Event Control
542(2)
C.2.5 begin-end
544(1)
C.2.6 if-then-else
545(1)
C.2.7 case, casex, casez
545(1)
C.2.8 for
546(1)
C.2.9 while
547(1)
C.2.10 function
547(1)
C.2.11 Behavioral Model Example
548(1)
C.3 Dataflow Model
548(2)
C.3.1 Continuous Assignment
549(1)
C.3.2 Conditional Assignment
549(1)
C.3.3 Dataflow Model Example
550(1)
C.4 Structural Model
550(3)
C.4.1 Built-in Gates
550(1)
C.4.2 User-Defined Module
551(2)
Appendix D VHDL Summary 553(25)
D.1 Basic Language Elements
553(11)
D.1.1 Keywords
553(1)
D.1.2 Comments
554(1)
D.1.3 Identifiers
554(1)
D.1.4 Data Objects
554(1)
D.1.5 Data Types
554(3)
D.1.6 Data Operators
557(1)
D.1.7 ENTITY
558(1)
D.1.8 ARCHITECTURE
559(1)
D.1.9 GENERIC
560(2)
D.1.10 PACKAGE
562(2)
D.2 Behavioral Model-Sequential Statements
564(6)
D.2.1 PROCESS
564(1)
D.2.2 Sequential Signal Assignment
564(1)
D.2.3 Variable Assignment
565(1)
D.2.4 WAIT
565(1)
D.2.5 IF-THEN-ELSE
565(1)
D.2.6 CASE
566(1)
D.2.7 NULL
566(1)
D.2.8 FOR
567(1)
D.2.9 WHILE
567(1)
D.2.10 LOOP
567(1)
D.2.11 EXIT
567(1)
D.2.12 NEXT
567(1)
D.2.13 FUNCTION
568(1)
D.2.14 PROCEDURE
569(1)
D.2.15 Behavioral Model Example
570(1)
D.3 Dataflow Model-Concurrent Statements
570(3)
D.3.1 Concurrent Signal Assignment
570(1)
D.3.2 Conditional Signal Assignment
571(1)
D.3.3 Selected Signal Assignment
571(1)
D.3.4 Dataflow Model Example
572(1)
D.4 Structural Model-Concurrent Statements
573(3)
D.4.1 COMPONENT Declaration
573(1)
D.4.2 PORT MAP
574(1)
D.4.3 OPEN
574(1)
D.4.4 GENERATE
575(1)
D.4.5 Structural Model Example
575(1)
D.5 Conversion Routines
576(2)
D.5.1 CONV_INTEGER()
576(1)
D.5.2 CONV_STD_LOGIC_VECTOR(,)
577(1)
Index 578