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Digital Sys Design Using Vhdl 2nd ed. [Raamat]

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  • Formaat: Book, 580 pages, Illustrations
  • Ilmumisaeg: 01-Feb-2007
  • Kirjastus: Brooks/Cole
  • ISBN-10: 0534384625
  • ISBN-13: 9780534384623
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Digital Sys Design Using Vhdl 2nd ed.Suurem pilt
  • Formaat: Book, 580 pages, Illustrations
  • Ilmumisaeg: 01-Feb-2007
  • Kirjastus: Brooks/Cole
  • ISBN-10: 0534384625
  • ISBN-13: 9780534384623
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780534384623.html
Märksõnad:
Written for an advanced-level course in digital systems design, DIGITAL SYSTEMS DESIGN USING VHDL integrates the use of the industry-standard hardware description language VHDL into the digital design process. Following a review of basic concepts of logic design, the author introduces the basics of VHDL, and then incorporates more coverage of advanced VHDL topics. Rather than simply teach VHDL as a programming language, this book emphasizes the practical use of VHDL in the digital design process.
Preface vii
Review of Logic Design Fundamentals
1(50)
Combinational Logic
1(2)
Boolean Algebra and Algebraic Simplification
3(4)
Karnaugh Maps
7(4)
Designing with NAND and NOR Gates
11(1)
Hazards in Combinational Circuits
12(2)
Flip-Flops and Latches
14(3)
Mealy Sequential Circuit Design
17(8)
Moore Sequential Circuit Design
25(3)
Equivalent States and Reduction of State Tables
28(2)
Sequential Circuit Timing
30(11)
Tristate Logic and Busses
41(10)
Introduction to VHDL
51(86)
Computer-Aided Design
51(3)
Hardware Description Languages
54(3)
VHDL Description of Combinational Circuits
57(4)
VHDL Modules
61(6)
Sequential Statements and VHDL Processes
67(2)
Modeling Flip-Flops Using VHDL Processes
69(4)
Processes Using Wait Statements
73(2)
Two Types of VHDL Delays: Transport and Inertial Delays
75(2)
Compilation, Simulation, and Synthesis of VHDL Code
77(5)
VHDL Data Types and Operators
82(2)
Simple Synthesis Examples
84(3)
VHDL Models for Multiplexers
87(3)
VHDL Libraries
90(5)
Modeling Registers and Counters Using VHDL Processes
95(6)
Behavioral and Structural VHDL
101(10)
Variables, Signals, and Constants
111(3)
Arrays
114(3)
Loops in VHDL
117(2)
Assert and Report Statements
119(18)
Introduction to Programmable Logic Devices
137(53)
Brief Overview of Programmable Logic Devices
137(3)
Simple Programmable Logic Devices (SPLDs)
140(16)
Complex Programmable Logic Devices (CPLDs)
156(4)
Field-Programmable Gate Arrays (FPGAs)
160(30)
Design Examples
190(70)
BCD to 7-Segment Display Decoder
191(1)
A BCD Adder
192(2)
32-Bit Adders
194(7)
Traffic Light Controller
201(3)
State Graphs for Control Circuits
204(1)
Scoreboard and Controller
205(3)
Synchronization and Debouncing
208(2)
A Shift-and-Add Multiplier
210(6)
Array Multiplier
216(3)
A Signed Integer/Fraction Muliplier
219(12)
Keypad Scanner
231(8)
Binary Dividers
239(21)
SM Charts and Microprogramming
260(50)
State Machine Charts
260(5)
Derivation of SM Charts
265(10)
Realization of SM Charts
275(4)
Implementation of the Dice Game
279(4)
Microprogramming
283(14)
Linked State Machines
297(13)
Designing with Field Programmable Gate Arrays
310(51)
Implementing Functions in FPGAs
310(6)
Implementing Functions Using Shannon's Decomposition
316(5)
Carry Chains in FPGAs
321(2)
Cascade Chains in FPGAs
323(1)
Examples of Logic Blocks in Commercial FPGAs
324(2)
Dedicated Memory in FPGAs
326(6)
Dedicated Multipliers in FPGAs
332(1)
Cost of Programmability
333(2)
FPGAs and One-Hot State Assignment
335(2)
FPGA Capacity: Maximum Gates Versus Usable Gates
337(1)
Design Translation (Synthesis)
338(11)
Mapping, Placement, and Routing
349(12)
Floating-Point Arithmetic
361(28)
Representation of Floating-Point Numbers
361(6)
Floating-Point Multiplication
367(10)
Floating-Point Addition
377(6)
Other Floating-Point Operations
383(6)
Additional Topics in VHDL
389(40)
VHDL Functions
389(4)
VHDL Procedures
393(2)
Attributes
395(4)
Creating Overloaded Operators
399(1)
Multi-Valued Logic and Signal Resolution
400(5)
The IEEE 9-Valued Logic System
405(3)
SRAM Model Using IEEE 1164
408(2)
Model for SRAM Read/Write System
410(3)
Generics
413(1)
Named Association
414(1)
Generate Statements
415(2)
Files and TEXTIO
417(12)
Design of a RISC Microprocessor
429(39)
The RISC Philosophy
429(3)
The MIPS ISA
432(6)
MIPS Instruction Encoding
438(3)
Implementation of a MIPS Subset
441(8)
VHDL Model
449(19)
Hardware Testing and Design for Testability
468(39)
Testing Combinational Logic
468(5)
Testing Sequential Logic
473(3)
Scan Testing
476(3)
Boundary Scan
479(11)
Built-In Self-Test
490(17)
Additional Design Examples
507(38)
Design of a Wristwatch
507(11)
Memory Timing Models
518(8)
A Universal Asynchronous Receiver Transmitter (UART)
526(19)
Appendix A VHDL Language Summary 545(8)
Appendix B IEEE Standard Libraries 553(2)
Appendix C TEXTIO Package 555(2)
Appendix D Projects 557(11)
References 568(3)
Index 571