Preface |
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xvii | |
Abbreviations |
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xxiii | |
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Introduction to Programmable Logic |
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1 | (42) |
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1 | (9) |
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Electronic Circuits: Analogue and Digital |
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10 | (4) |
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10 | (1) |
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Continuous Time versus Discrete Time |
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10 | (2) |
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12 | (2) |
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14 | (3) |
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Programmable Logic versus Discrete Logic |
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17 | (4) |
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Programmable Logic versus Processors |
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21 | (3) |
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Types of Programmable Logic |
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24 | (5) |
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Simple Programmable Logic Device (SPLD) |
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24 | (3) |
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Complex Programmable Logic Device (CPLD) |
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27 | (1) |
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Field Programmable Gate Array (FPGA) |
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28 | (1) |
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PLD Configuration Technologies |
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29 | (3) |
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Programmable Logic Vendors |
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32 | (1) |
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Programmable Logic Design Methods and Tools |
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33 | (3) |
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33 | (2) |
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35 | (1) |
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36 | (7) |
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38 | (2) |
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40 | (3) |
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Electronic Systems Design |
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43 | (80) |
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43 | (9) |
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Sequential Product Development Process versus Concurrent Engineering Process |
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52 | (4) |
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52 | (1) |
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Sequential Product Development Process |
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53 | (1) |
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Concurrent Engineering Process |
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54 | (2) |
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56 | (2) |
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58 | (3) |
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61 | (1) |
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Hardware-Software Co-Design |
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62 | (3) |
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65 | (1) |
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Embedded Systems and Real-Time Operating Systems |
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66 | (1) |
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Electronic System-Level Design |
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67 | (1) |
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Creating a Design Specification |
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68 | (2) |
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Unified Modeling Language |
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70 | (2) |
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Reading a Component Data Sheet |
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72 | (3) |
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75 | (14) |
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75 | (4) |
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79 | (2) |
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81 | (2) |
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Interfacing Logic Families |
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83 | (6) |
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Parallel and Serial Interfacing |
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89 | (13) |
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89 | (6) |
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95 | (2) |
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97 | (5) |
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102 | (3) |
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105 | (2) |
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107 | (2) |
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109 | (1) |
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Printed Circuit Boards and Multichip Modules |
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110 | (2) |
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System on a Chip and System in a Package |
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112 | (1) |
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113 | (2) |
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115 | (1) |
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116 | (7) |
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118 | (3) |
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121 | (2) |
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123 | (54) |
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123 | (2) |
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125 | (19) |
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125 | (2) |
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127 | (12) |
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139 | (5) |
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Design, Manufacture, and Testing |
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144 | (8) |
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144 | (6) |
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150 | (1) |
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151 | (1) |
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152 | (3) |
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152 | (1) |
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153 | (1) |
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153 | (1) |
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154 | (1) |
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Electromagnetic Compatibility |
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154 | (1) |
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155 | (16) |
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155 | (2) |
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157 | (1) |
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158 | (2) |
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160 | (3) |
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163 | (3) |
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166 | (2) |
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168 | (3) |
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171 | (6) |
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173 | (2) |
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175 | (2) |
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177 | (40) |
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177 | (1) |
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Software Programming Languages |
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177 | (16) |
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177 | (2) |
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179 | (2) |
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181 | (2) |
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183 | (3) |
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186 | (3) |
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189 | (2) |
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191 | (2) |
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Hardware Description Languages |
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193 | (12) |
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193 | (1) |
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194 | (2) |
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196 | (3) |
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199 | (3) |
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202 | (3) |
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205 | (1) |
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205 | (3) |
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208 | (1) |
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209 | (1) |
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Mathematical Modeling Tools |
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210 | (7) |
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214 | (2) |
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216 | (1) |
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Introduction to Digital Logic Design |
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217 | (116) |
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217 | (5) |
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222 | (18) |
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222 | (2) |
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Decimal--Unsigned Binary Conversion |
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224 | (2) |
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226 | (5) |
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231 | (1) |
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232 | (1) |
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233 | (2) |
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Hexadecimal-Binary Conversion |
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235 | (5) |
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240 | (16) |
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240 | (1) |
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241 | (1) |
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242 | (4) |
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Combinational Logic Gates |
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246 | (2) |
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248 | (8) |
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Combinational Logic Design |
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256 | (21) |
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256 | (13) |
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269 | (2) |
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271 | (6) |
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277 | (1) |
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277 | (45) |
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277 | (5) |
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Level Sensitive Latches and Edge-Triggered Flip-Flops |
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282 | (1) |
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The D Latch and D-Type Flip-Flop |
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283 | (5) |
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288 | (17) |
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305 | (11) |
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Moore versus Mealy State Machines |
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316 | (1) |
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317 | (2) |
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319 | (3) |
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322 | (11) |
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322 | (2) |
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324 | (1) |
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325 | (2) |
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327 | (1) |
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328 | (5) |
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Introduction to Digital Logic Design with VHDL |
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333 | (142) |
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333 | (1) |
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334 | (4) |
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338 | (3) |
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338 | (1) |
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338 | (1) |
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339 | (2) |
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341 | (3) |
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Entities, Architectures, Packages, and Configurations |
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344 | (11) |
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344 | (2) |
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346 | (7) |
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353 | (2) |
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355 | (11) |
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355 | (1) |
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Dataflow Description Example |
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356 | (1) |
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Behavioral Description Example |
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357 | (2) |
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Structural Description Example |
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359 | (7) |
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366 | (8) |
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366 | (2) |
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Example: Architecture with Internal Signals |
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368 | (4) |
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Example: Architecture with Internal Variables |
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372 | (2) |
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374 | (6) |
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380 | (1) |
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380 | (3) |
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Concurrent versus Sequential Statements |
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383 | (1) |
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Loops and Program Control |
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383 | (2) |
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385 | (2) |
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Combinational Logic Design |
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387 | (27) |
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387 | (1) |
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388 | (1) |
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388 | (1) |
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389 | (8) |
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Thermometer-to-Binary Encoder |
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397 | (1) |
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Seven-Segment Display Driver |
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398 | (11) |
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409 | (5) |
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414 | (26) |
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414 | (2) |
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416 | (6) |
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422 | (4) |
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426 | (14) |
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440 | (7) |
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440 | (1) |
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441 | (3) |
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444 | (3) |
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Unsigned versus Signed Arithmetic |
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447 | (6) |
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447 | (1) |
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448 | (1) |
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449 | (4) |
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Testing the Design: The VHDL Test Bench |
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453 | (6) |
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File I/O for Test Bench Development |
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459 | (16) |
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471 | (1) |
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472 | (3) |
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Introduction to Digital Signal Processing |
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475 | (62) |
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475 | (21) |
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496 | (13) |
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509 | (15) |
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524 | (13) |
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524 | (8) |
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Infinite Impulse Response Filters |
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532 | (2) |
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Finite Impulse Response Filters |
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534 | (1) |
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535 | (1) |
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536 | (1) |
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Interfacing Digital Logic to the Real World: A/D Conversion, D/A Conversion, and Power Electronics |
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537 | (78) |
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537 | (6) |
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Digital-to-Analogue Conversion |
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543 | (22) |
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543 | (5) |
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548 | (7) |
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555 | (4) |
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559 | (6) |
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Analogue-to-Digital Conversion |
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565 | (15) |
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565 | (3) |
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568 | (4) |
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572 | (5) |
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577 | (3) |
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580 | (26) |
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580 | (1) |
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581 | (4) |
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585 | (8) |
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593 | (10) |
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603 | (1) |
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604 | (1) |
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604 | (2) |
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Heat Dissipation and Heatsinks |
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606 | (4) |
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Operational Amplifier Circuits |
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610 | (5) |
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612 | (1) |
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613 | (2) |
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Testing the Electronic System |
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615 | (32) |
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615 | (6) |
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Integrated Circuit Testing |
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621 | (12) |
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621 | (3) |
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624 | (5) |
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629 | (4) |
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633 | (1) |
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Printed Circuit Board Testing |
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633 | (3) |
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636 | (6) |
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642 | (5) |
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645 | (1) |
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646 | (1) |
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647 | (60) |
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647 | (7) |
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Electronic System-Level Design |
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654 | (7) |
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Case Study 1: DC Motor Control |
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661 | (25) |
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661 | (1) |
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Motor Control System Overview |
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662 | (3) |
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MATLAB®/Simulink® Model Creation and Simulation |
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665 | (1) |
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Translating the Design to VHDL |
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666 | (8) |
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674 | (12) |
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Case Study 2: Digital Filter Design |
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686 | (16) |
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686 | (2) |
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688 | (2) |
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MATLAB®/Simulink® Model Creation and Simulation |
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690 | (2) |
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Translating the Design to VHDL |
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692 | (6) |
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698 | (4) |
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Automating the Translation |
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702 | (1) |
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703 | (4) |
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704 | (1) |
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705 | (2) |
Additional References |
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707 | (10) |
Index |
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717 | |