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Digital Systems Design Using VHDL 3rd edition [Kõva köide]

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  • Formaat: Hardback, 592 pages, kõrgus x laius x paksus: 234x203x28 mm, kaal: 1202 g
  • Ilmumisaeg: 01-Jan-2017
  • Kirjastus: CENGAGE Learning Custom Publishing
  • ISBN-10: 1305635140
  • ISBN-13: 9781305635142
Teised raamatud teemal:
Digital Systems Design Using VHDL 3rd editionSuurem pilt
  • Formaat: Hardback, 592 pages, kõrgus x laius x paksus: 234x203x28 mm, kaal: 1202 g
  • Ilmumisaeg: 01-Jan-2017
  • Kirjastus: CENGAGE Learning Custom Publishing
  • ISBN-10: 1305635140
  • ISBN-13: 9781305635142
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781305635142.html
Written for an advanced-level course in digital systems design, Roth/John's DIGITAL SYSTEMS DESIGN USING VHDL, 3E integrates the use of the industry-standard hardware description language VHDL into the digital design process. The book begins with a valuable review of basic logic design concepts before introducing the fundamentals of VHDL. The book concludes with detailed coverage of advanced VHDL topics.
Preface vii
About the Authors xii
Chapter 1 Review of Logic Design Fundamentals
1(38)
1.1 Combinational Logic
1(2)
1.2 Boolean Algebra and Algebraic Simplification
3(4)
1.3 Karnaugh Maps
7(3)
1.4 Designing With NAND and NOR Gates
10(2)
1.5 Hazards in Combinational Circuits
12(4)
1.6 Flip-Flops and Latches
16(2)
1.7 Mealy Sequential Circuit Design
18(7)
1.8 Moore Sequential Circuit Design
25(3)
1.9 Equivalent States and Reduction of State Tables
28(2)
1.10 Sequential Circuit Timing
30(1)
1.11 Tristate Logic and Busses
31(8)
Problems
34(5)
Chapter 2 Introduction to VHDL
39(89)
2.1 Computer-Aided Design
39(3)
2.2 Hardware Description Languages
42(2)
2.3 VHDL Description of Combinational Circuits
44(3)
2.4 VHDL Modules
47(7)
2.5 Sequential Statements and VHDL Processes
54(1)
2.6 Modeling Flip-Flops Using VHDL Processes
55(4)
2.7 Processes Using Wait Statements
59(3)
2.8 Two Types of VHDL Delays: Transport and Inertial Delays
62(1)
2.9 Compilation, Simulation, and Synthesis of VHDL Code
63(4)
2.10 VHDL Data Types and Operators
67(2)
2.11 Simple Synthesis Examples
69(3)
2.12 VHDL Models for Multiplexers
72(3)
2.13 VHDL Libraries
75(4)
2.14 Modeling Registers and Counters Using VHDL Processes
79(6)
2.15 Behavioral and Structural VHDL
85(9)
2.16 Variables, Signals, and Constants
94(3)
2.17 Arrays
97(4)
2.18 Loops in VHDL
101(1)
2.19 Assert and Report Statements
102(4)
2.20 Tips for Debugging VHDL Code
106(22)
Problems
114(14)
Chapter 3 Introduction to Programmable Logic Devices
128(56)
3.1 Brief Overview of Programmable Logic Devices
128(3)
3.2 Simple Programmable Logic Devices
131(15)
3.3 Complex Programmable Logic Devices
146(4)
3.4 Field Programmable Gate Arrays
150(24)
3.5 Programmable SoCs (PSOC)
174(10)
Problems
176(8)
Chapter 4 Design Examples
184(72)
4.1 BCD to Seven-Segment Display Decoder
185(1)
4.2 A BCD Adder
186(2)
4.3 32-Bit Adders
188(10)
4.4 Traffic Light Controller
198(3)
4.5 State Graphs for Control Circuits
201(2)
4.6 Scoreboard and Controller
203(3)
4.7 Synchronization and Debouncing
206(2)
4.8 Add-and-Shift Multiplier
208(5)
4.9 Array Multiplier
213(3)
4.10 A Signed Integer/Fraction Multiplier
216(12)
4.11 Keypad Scanner
228(7)
4.12 Binary Dividers
235(21)
Problems
244(12)
Chapter 5 SM Charts and Microprogramming
256(52)
5.1 State Machine Charts
256(5)
5.2 Derivation of SM Charts
261(10)
5.3 Realization of SM Charts
271(3)
5.4 Implementation of the Dice Game
274(4)
5.5 Microprogramming
278(17)
5.6 Linked State Machines
295(13)
Problems
297(11)
Chapter 6 Designing with Field Programmable Gate
308(53)
6.1 Implementing Functions in FPGAs
308(6)
6.2 Implementing Functions Using Shannon's Decomposition
314(5)
6.3 Carry Chains in FPGAs
319(1)
6.4 Cascade Chains in FPGAs
320(2)
6.5 Examples of Logic Blocks in Commercial FPGAs
322(2)
6.6 Dedicated Memory in FPGAs
324(6)
6.7 Dedicated Multipliers in FPGAs
330(1)
6.8 Cost of Programmability
331(2)
6.9 FPGAs and One-Hot State Assignment
333(2)
6.10 FPGA Capacity: Maximum Gates versus Usable Gates
335(1)
6.11 Design Translation (Synthesis)
336(10)
6.12 Mapping, Placement, and Routing
346(15)
Problems
351(10)
Chapter 7 Floating-Point Arithmetic
361(30)
7.1 Representation of Floating-Point Numbers
361(9)
7.2 Floating-Point Multiplication
370(8)
7.3 Floating-Point Addition
378(7)
7.4 Other Floating-Point Operations
385(6)
Problems
386(5)
Chapter 8 Additional Topics in VHDL
391(42)
8.1 VHDL Functions
391(3)
8.2 VHDL Procedures
394(3)
8.3 VHDL Predefined Function Called NOW
397(1)
8.4 Attributes
398(4)
8.5 Creating Overloaded Operators
402(1)
8.6 Multivalued Logic and Signal Resolution
403(5)
8.7 The IEEE 9-Valued Logic System
408(4)
8.8 SRAM Model Using IEEE 1164
412(2)
8.9 Model for SRAM Read/Write System
414(3)
8.10 Generics
417(1)
8.11 Named Association
418(1)
8.12 Generate Statements
419(2)
8.13 Files and TEXTIO
421(12)
Problems
425(8)
Chapter 9 Design of RISC Microprocessors
433(82)
9.1 The RISC Philosophy
433(3)
9.2 The MIPS ISA
436(5)
9.3 MIPS Instruction Encoding
441(4)
9.4 Implementation of a MIPS Subset
445(6)
9.5 VHDL Model of the MIPS Subset
451(14)
9.6 Design of an ARM Processor
465(10)
9.7 ARM Instruction Encoding
475(8)
9.8 Implementation of a Subset of ARM Instructions
483(8)
9.9 VHDL Model of the ARM Subset
491(24)
Problems
509(6)
Chapter 10 Verification of Digital Systems
515(39)
10.1 Importance of Verification
515(4)
10.2 Verification Terminology
519(2)
10.3 Functional Verification
521(5)
10.4 Timing Verification
526(2)
10.5 Static Timing Analysis for Circuits with No Skew
528(7)
10.6 Static Timing Analysis for Circuits with Clock Skew
535(4)
10.7 Glitches in Sequential Circuits
539(1)
10.8 Clock Gating
540(4)
10.9 Clock Distribution Circuitry
544(10)
Problems
546(8)
Chapter 11 Hardware Testing and Design for Testability
554(42)
11.1 Faults and Fault Models
555(1)
11.2 Testing Combinational Logic
556(4)
11.3 Testing Sequential Logic
560(4)
11.4 Scan Testing
564(2)
11.5 Boundary Scan
566(11)
11.6 Memory Testing
577(2)
11.7 Built-in Self-Test
579(17)
Problems
589(7)
Chapter 12 Additional Design Examples (Online)
Appendix A VHDL Language Summary 596(8)
Appendix B IEEE Standard Libraries 604(2)
Appendix C TEXTIO Package 606(2)
Appendix D Projects 608(10)
References 618(4)
Index 622