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Digitally-Assisted Analog and Analog-Assisted Digital IC Design [Kõva köide]

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  • Formaat: Hardback, 413 pages, kõrgus x laius x paksus: 252x180x23 mm, kaal: 970 g, 30 Tables, black and white; 60 Halftones, unspecified; 267 Line drawings, unspecified
  • Ilmumisaeg: 23-Jul-2015
  • Kirjastus: Cambridge University Press
  • ISBN-10: 1107096103
  • ISBN-13: 9781107096103
Teised raamatud teemal:
Digitally-Assisted Analog and Analog-Assisted Digital IC DesignSuurem pilt
  • Formaat: Hardback, 413 pages, kõrgus x laius x paksus: 252x180x23 mm, kaal: 970 g, 30 Tables, black and white; 60 Halftones, unspecified; 267 Line drawings, unspecified
  • Ilmumisaeg: 23-Jul-2015
  • Kirjastus: Cambridge University Press
  • ISBN-10: 1107096103
  • ISBN-13: 9781107096103
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781107096103.html
Märksõnad:
Achieve enhanced performance with this guide to cutting-edge techniques for digitally-assisted analog and analog-assisted digital integrated circuit design. • Discover how architecture and circuit innovations can deliver improved performance in terms of speed, density, power, and cost • Learn about practical design considerations for high-performance scaled CMOS processes, FinFet devices and architectures, and the implications of FD SOI technology • Get up to speed with established circuit techniques that take advantage of scaled CMOS process technology in analog, digital, RF and SoC designs, including digitally-assisted techniques for data converters, DSP enabled frequency synthesizers, and digital controllers for switching power converters. With detailed descriptions, explanations, and practical advice from leading industry experts, this is an ideal resource for practicing engineers, researchers, and graduate students working in circuit design.

Discover cutting-edge techniques for next-generation integrated circuit design, and deliver enhanced circuit performance in terms of speed, density, power, and cost. Written by leading experts in the field, this is an ideal resource for practicing engineers, graduate students, and researchers working in circuit design.

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Discover cutting-edge techniques for next-generation integrated circuit design, and learn how to deliver improved speed, density, power, and cost.
List of Contributors xiii
Preface xv
1 CMOS technology scaling and its implications 1(20)
1.1 Scaling theory and technology roadmap
2(3)
1.2 Short-channel effects
5(4)
1.2.1 Threshold voltage dependence on channel length
6(1)
1.2.2 Drain-induced barrier lowering (DIBL)
7(1)
1.2.3 Velocity saturation
8(1)
1.3 Scaling impact on power consumption
9(2)
1.4 Parasitic elements in front- and back-end processes
11(1)
1.5 Process variabilities
12(3)
1.6 Other implications in advanced processes
15(3)
1.6.1 Layout-dependent performance variation
15(2)
1.6.2 Reliability concerns
17(1)
References
18(3)
2 FinFETs: from devices to architectures 21(35)
2.1 Introduction
21(2)
2.2 FinFETs
23(9)
2.2.1 FinFET classification
25(4)
2.2.2 Process variations
29(3)
2.3 FinFET device characterization
32(2)
2.3.1 Process simulation
33(1)
2.3.2 Device simulation
33(1)
2.3.3 Compact models
34(1)
2.4 FinFET standard cells
34(9)
2.4.1 SG/IG INV
35(1)
2.4.2 SG/IG NAND2
36(1)
2.4.3 ASG logic gates
36(1)
2.4.4 SG/IG/ASG latches and flip-flops
37(2)
2.4.5 SRAM
39(3)
2.4.6 DRAM
42(1)
2.5 Circuit-level analysis
43(2)
2.5.1 Analysis
43(1)
2.5.2 Optimization
43(1)
2.5.3 Novel interconnect structures and logic synthesis
43(2)
2.6 Architecture-level analysis
45(3)
2.6.1 FinFET-based caches
45(1)
2.6.2 FinFET-based NoCs
45(1)
2.6.3 FinFET-based multicore processors
46(2)
2.7 Conclusion
48(1)
Acknowledgements
49(1)
References
49(7)
3 FDSOI technology and its implications for analog and digital design 56(42)
3.1 CMOS scaling and FDSOI structure
56(5)
3.1.1 FDSOI structure
58(3)
3.2 FDSOI device design
61(10)
3.2.1 Performance
61(2)
3.2.2 Parasitic resistance
63(1)
3.2.3 Parasitic capacitance
64(2)
3.2.4 Carrier mobility and strain engineering
66(4)
3.2.5 Desired short-channel control
70(1)
3.3 FDSOI manufacturing challenges and solutions
71(9)
3.3.1 FDSOI substrates
71(3)
3.3.2 Manufacturing challenges
74(6)
3.4 Circuit design in FDSOI
80(8)
3.4.1 Multi-VT options in FDSOI
80(3)
3.4.2 Body biasing in FDSOI
83(1)
3.4.3 Ultra-low-voltage design in FDSOI
84(1)
3.4.4 SRAM implementation
85(2)
3.4.5 Implications for analog designs
87(1)
3.4.6 Hybrid bulk-FDSOI integration
88(1)
3.5 FDSOI scalability and global landscape
88(5)
3.5.1 Global FDSOI landscape
92(1)
References
93(5)
4 Challenges and emerging trends of DSP-enabled frequency synthesizers 98(37)
4.1 Introduction
98(4)
4.1.1 Overheads in digital PLL designs
100(2)
4.2 DPLL architecture
102(4)
4.2.1 Fractional-N DPLL architectures
102(4)
4.2.2 Integer-N DPLL architectures
106(1)
4.3 DPLL building blocks
106(11)
4.3.1 Digitally controlled oscillators
107(2)
4.3.2 Time-to-digital converter
109(5)
4.3.3 Loop filter
114(3)
4.4 Emerging techniques beyond analog PLL capability: adaptive spur cancellation
117(3)
4.5 Design examples
120(11)
4.5.1 DPLL for baseband clocking in 65 nm CMOS
120(7)
4.5.2 DPLL for LO synthesis in 65 nm CMOS
127(4)
4.6 Conclusion
131(1)
References
132(3)
5 Digitally-assisted design of data converters 135(39)
5.1 Overview and historic remarks
135(8)
5.1.1 Background vs. foreground calibration
135(2)
5.1.2 Digital-domain calibration
137(1)
5.1.3 History of background calibration
138(5)
5.2 Linearity calibration of pipelined ADC
143(15)
5.2.1 The error model
143(4)
5.2.2 Error-parameter identification
147(11)
5.3 Linearity calibration of SAR ADC
158(10)
5.3.1 The error model of sub-binary SAR ADC
160(3)
5.3.2 Error-parameter identification
163(5)
5.4 Convergence speed of background calibration
168(1)
References
169(5)
6 CMOS self-healing techniques for calibration and optimization of mm-wave transceivers 174(23)
6.1 Challenges of process variation at mm-wave
174(1)
6.2 Actuators, sensors, and self-healing techniques for optimizing transmitter output power and transceiver linearity
175(10)
6.2.1 Transmitter actuators
175(1)
6.2.2 Transmitter feedback sensors
176(2)
6.2.3 Transmitter power and single-tone transmitter linearity calibration
178(4)
6.2.4 Two-tone transmitter linearity calibration with envelope sensing
182(2)
6.2.5 Two-tone receiver linearity calibration
184(1)
6.3 Actuators, sensors, and self-healing techniques for optimizing transceiver carrier distortion and noise
185(7)
6.3.1 Sensors and actuators for calibration of IQ mismatch
186(2)
6.3.2 Algorithms for calibration of IQ mismatch
188(1)
6.3.3 Sensors and actuators for calibration of LO feed-through
189(1)
6.3.4 Noise estimation and calibration of the receiver
190(2)
6.4 Calibration of mm-wave VCOs for wideband frequency synthesizers
192(3)
6.4.1 Digitally controlled artificial dielectric (DiCAD) actuators
192(1)
6.4.2 Self-locking algorithm for DiCAD-based PLLs
193(2)
References
195(2)
7 Analog-assisted digital design in mobile SoCs 197(45)
7.1 Digital design challenges for mobile SoCs
197(6)
7.1.1 Energy efficiency
197(1)
7.1.2 Process variability
198(1)
7.1.3 Power-supply noise
199(1)
7.1.4 Thermal management
200(1)
7.1.5 Aging
201(2)
7.2 Adaptive voltage scaling
203(4)
7.2.1 Open-loop voltage scaling
203(1)
7.2.2 Closed-loop voltage scaling
203(1)
7.2.3 Speed sensors
204(1)
7.2.4 Critical-path synthesis
204(2)
7.2.5 Error detection and correction
206(1)
7.3 Voltage regulation
207(14)
7.3.1 Buck regulator
207(4)
7.3.2 Low-dropout regulator
211(6)
7.3.3 Switched-capacitor converter
217(4)
7.4 Voltage droop management
221(7)
7.4.1 Voltage droop detection
222(1)
7.4.2 Active decoupling
223(4)
7.4.3 Adaptive clocking
227(1)
7.5 Inrush current management
228(7)
7.5.1 Power switches
229(1)
7.5.2 Model for power-delivery network
230(2)
7.5.3 Minimizing noise when turning a switch on or off
232(3)
7.6 Temperature and aging sensors
235(4)
7.6.1 Temperature sensors
235(3)
7.6.2 Aging sensors
238(1)
References
239(3)
8 Digitally-assisted RF design techniques 242(81)
8.1 Introduction
242(1)
8.2 Overview of digitally-assisted correction strategies
243(8)
8.2.1 Model-feedback block diagrams
244(1)
8.2.2 Actuators
245(1)
8.2.3 Sensors
246(2)
8.2.4 Loop filters
248(2)
8.2.5 Correction in receivers vs. transmitters
250(1)
8.2.6 Dither and shuffling
251(1)
8.3 Communication links and transceivers — block diagrams
251(4)
8.3.1 Communication links
251(1)
8.3.2 Receivers and transmitters
252(3)
8.4 Dynamic range specifications
255(2)
8.4.1 Sensitivity: noise limitation
255(1)
8.4.2 Selectivity/blocker tolerance: clipping and linearity limitation
256(1)
8.4.3 Transceiver dynamic range planning
256(1)
8.5 Behavior of RF cascades
257(6)
8.5.1 Friis equation
257(1)
8.5.2 Distortion and clipping in cascades
258(2)
8.5.3 Nonlinear circuits with memory
260(3)
8.6 Fundamental limitations of RF stages
263(2)
8.6.1 What determines amplifier power? Noise, distortion, BW or RF output power?
263(1)
8.6.2 Amplifier classes and efficiency
264(1)
8.7 ADCs as RF blocks
265(12)
8.7.1 ADC impairments
265(3)
8.7.2 NF, intercept, and compression points
268(1)
8.7.3 Noise power ratio (NPR)
268(1)
8.7.4 Impact of ADC imperfections on communication signals and systems
269(8)
8.8 DACs as RF blocks
277(4)
8.8.1 Direct-sampling transmitter block diagram
277(1)
8.8.2 Noise, distortion, and images
277(1)
8.8.3 Efficiency and underlying amplifier classes
278(1)
8.8.4 Digital drive power
278(1)
8.8.5 Power DACs versus power amplifiers
279(2)
8.9 Phase noise
281(7)
8.9.1 Additive noise vs. multiplicative noise
281(1)
8.9.2 Impact of phase noise on communication systems
281(2)
8.9.3 Typical PLL phase noise characteristics
283(2)
8.9.4 Phase noise in heterodyne vs. direct-sampling systems
285(3)
8.10 Impairments and digitally-assisted mitigation in heterodyne transceivers
288(10)
8.10.1 Sideband images and IQ balance
288(5)
8.10.2 LO harmonic images
293(5)
8.11 Impairments and digitally-assisted mitigation in direct-sampling transceivers
298(10)
8.11.1 Time-domain equalizers vs. frequency-domain cancelers for mitigation
298(1)
8.11.2 Lane imbalance
299(4)
8.11.3 Distortion
303(1)
8.11.4 Digital correction in pipeline ADCs
303(5)
8.12 Transmitter leakage and other ingress cancelers
308(1)
8.12.1 Transmitter ingress
308(1)
8.12.2 Pickup
309(1)
8.13 Digital vs. analog area and power
309(5)
8.13.1 Trends and limits
312(1)
8.13.2 How much DSP is needed for different strategies?
313(1)
8.13.3 Optimizing digital dynamic range for lower area and power
314(1)
8.14 Variable-dynamic-range front ends
314(2)
8.15 Conclusion
316(1)
Acknowledgements
316(1)
References
317(6)
9 Digital controllers for switching power converters 323(69)
9.1 Basic operations of a buck converter system
323(1)
9.2 Digital controllers versus analog controllers
324(3)
9.2.1 Motivation for using a digital controller
324(1)
9.2.2 Digital current-mode controllers versus digital voltage-mode controllers
325(2)
9.3 Analog-to-digital converter for digital controllers
327(10)
9.3.1 Common ADC for digital controllers
327(3)
9.3.2 Design of time-multiplex ADC
330(7)
9.4 Digital pulse-width modulator (DPWM)
337(3)
9.5 Digital compensation network
340(4)
9.5.1 DSP/FPGA/microcontroller approach
340(1)
9.5.2 Look-up-table (LUT) approach
341(1)
9.5.3 Custom-made digital circuit approach
341(1)
9.5.4 Look-up-table with table reduction techniques
342(2)
9.6 Inductor current-sensing for digital controllers
344(18)
9.6.1 Conventional inductor current-sensing and quantization
346(2)
9.6.2 Digital inductor current sensor
348(7)
9.6.3 Measurement results and discussion
355(7)
9.7 Advanced digital current-mode controllers (DCMCs)
362(24)
9.7.1 Inductor current-sensing for ripple-based DC-DC converters
362(1)
9.7.2 Analysis of the analog and digital inductor current sensor
363(8)
9.7.3 Design and implementation of a digital inductor current sensor for ripple-based digital controllers
371(8)
9.7.4 Measurement results and discussion
379(7)
9.8 Summary
386(1)
References
386(6)
Appendix A 392(2)
Appendix B 394(1)
Index 395
Xicheng Jiang is Distinguished Engineer and Director of Electrical Design Engineering at Broadcom Corporation. He is a former Associate Editor of IEEE Transactions on Circuits and Systems II, holds more than 30 issued and pending US patents, and is a Fellow of the IEEE.