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Three-Dimensional Design Methodologies for Tree-based FPGA Architecture 2015 ed. [Kõva köide]

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  • Formaat: Hardback, 226 pages, kõrgus x laius: 235x155 mm, kaal: 633 g, 102 Illustrations, color; 11 Illustrations, black and white; XXI, 226 p. 113 illus., 102 illus. in color., 1 Hardback
  • Sari: Lecture Notes in Electrical Engineering 350
  • Ilmumisaeg: 08-Jul-2015
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 331919173X
  • ISBN-13: 9783319191737
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Three-Dimensional Design Methodologies for Tree-based FPGA Architecture 2015 ed.Suurem pilt
  • Formaat: Hardback, 226 pages, kõrgus x laius: 235x155 mm, kaal: 633 g, 102 Illustrations, color; 11 Illustrations, black and white; XXI, 226 p. 113 illus., 102 illus. in color., 1 Hardback
  • Sari: Lecture Notes in Electrical Engineering 350
  • Ilmumisaeg: 08-Jul-2015
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 331919173X
  • ISBN-13: 9783319191737
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783319191737.html
Märksõnad:

This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as,the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and professionals alike.

1 An Overview of Three-Dimensional Integration and FPGAs
1(12)
1.1 Introduction
1(4)
1.1.1 More Moore (MM)
2(1)
1.1.2 More Than Moore (MtM)
3(2)
1.2 Technological Initiatives and Contribution
5(5)
1.2.1 Modified Tree-Based Interconnect
7(1)
1.2.2 Tree-Based Interconnect Partitioning
7(1)
1.2.3 3D FPGA Design and Implementation Methodology
8(1)
1.2.4 Unified Mesh of Tree Architecture
9(1)
1.3 Book Organization
10(3)
References
11(2)
2 Three-Dimensional Integration: A More Than Moore Technology
13(30)
2.1 Introduction
13(3)
2.1.1 Opportunities for Three-Dimensional Integration
14(2)
2.2 Historical Evolution of 3D System Integration
16(3)
2.3 Vertical Interconnect Technology Development (TSV)
19(2)
2.4 3D Integration: Manufacturing Methods
21(3)
2.5 Challenges in 3D Physical Design
24(11)
2.5.1 Complexity of 3D Physical Design Tools and Their Limitations
25(1)
2.5.2 TSV and Thermal Management
26(1)
2.5.3 Power and Clock Delivery in 3D-ICs
27(1)
2.5.4 TSV-Induced Design for Manufacturability Issues
28(1)
2.5.5 Floorplanning for 3D Circuits
28(1)
2.5.6 Placement for 3D Circuits
29(3)
2.5.7 Routing for 3D Circuits
32(3)
2.6 3D-IC Design Verification
35(1)
2.7 Summary
36(7)
References
37(6)
3 Field Programmable Gate Arrays: An Overview
43(30)
3.1 Introduction
43(1)
3.2 Introduction to FPGA Architectures
44(4)
3.2.1 Configurable Logic Blocks
45(3)
3.3 FPGA Interconnect Topologies
48(8)
3.3.1 Mesh-Based Interconnect Network
48(1)
3.3.2 FPGA Switch Block
49(2)
3.3.3 FPGA Routing Channels
51(2)
3.3.4 Multilevel Hierarchical Interconnect
53(3)
3.4 Proposed FPGA Interconnect Architectures
56(3)
3.4.1 Evolution of Tree-Based Interconnect Architecture
56(2)
3.4.2 Wire Growth Model
58(1)
3.4.3 Switch Growth Model
58(1)
3.5 Tree-Based Routing Interconnect
59(4)
3.5.1 Tree-Based FPGA Architecture
61(2)
3.6 Unified Mesh- and Tree-Based Interconnect
63(6)
3.6.1 Cluster Local Interconnect
65(1)
3.6.2 Mesh-Based Routing Interconnect
66(2)
3.6.3 Input and Output Pads Connection
68(1)
3.7 Summary
69(4)
References
69(4)
4 Two Dimensional FPGAs: Configuration and CAD Flow
73(22)
4.1 Introduction
73(1)
4.2 Circuit Synthesis
74(1)
4.3 Technology Mapping
74(1)
4.4 Clustering
75(7)
4.4.1 Bottom-Up Approaches
77(1)
4.4.2 Top-Down Approaches
78(4)
4.5 Placement
82(3)
4.5.1 Simulated Annealing Based Approach
83(1)
4.5.2 Partitioning Based Approach
84(1)
4.6 Routing
85(2)
4.7 Two-Dimensional CAD for Tree-Based Architecture
87(5)
4.7.1 Synthesis and Mapping
88(1)
4.7.2 Clustering and Partitioning
88(4)
4.8 Timing Analysis
92(1)
4.9 Summary
93(2)
References
93(2)
5 Three-Dimensional FPGAs: Configuration and CAD Development
95(22)
5.1 Introduction
95(1)
5.2 3D FPGA Architectures: An Overview
96(3)
5.2.1 FPGA Die Stacking
96(2)
5.2.2 Monolithic FPGA Implementation
98(1)
5.3 State-of-the-Art: 3D FPGA Implementation
99(5)
5.4 3D FPGA Interconnect Switch
104(3)
5.5 2.5D Integration: High Density Multi-FPGAs
107(4)
5.5.1 Industrial 2.5D Virtex-7 Interposer-Based FPGAs
109(2)
5.6 Development of 3D Tree-Based FPGA CAD Tools
111(3)
5.6.1 3D FPGA Physical Design Tools
111(2)
5.6.2 3D FPGA Architecture Exploration and Optimization
113(1)
5.7 Summary
114(3)
References
114(3)
6 Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and Technologies
117(30)
6.1 Introduction
117(1)
6.2 Tree-Based FPGA Interconnect Architecture
118(3)
6.2.1 2D Tree-Based Interconnect: A Comparison with 2D Mesh-Based Interconnect
119(2)
6.3 Tree-Based Interconnect Partitioning
121(4)
6.3.1 Vertical Partitioning
122(1)
6.3.2 Horizontal Partitioning
123(1)
6.3.3 Through Silicon via (TSV) Modeling
124(1)
6.4 3D Tree-Based Interconnect Optimization Methodology
125(1)
6.5 Interconnect Optimization: Homogeneous Tree
126(6)
6.5.1 The Downward Programmable Network Model
127(1)
6.5.2 The Upward Programmable Network Model
127(5)
6.6 Heterogeneous Tree-Based FPGA Architecture
132(4)
6.6.1 Interconnect Optimization: Heterogeneous Tree
134(2)
6.7 Critical Path Delay Analysis
136(4)
6.7.1 Delay Analysis: Homogeneous Tree
136(2)
6.7.2 Delay Analysis: Heterogeneous Tree
138(2)
6.8 LUT and Cluster Size Effect on Performance
140(3)
6.9 Power Optimization
143(2)
6.10 Summary
145(2)
References
145(2)
7 Three-Dimensional Thermal Modeling: Tools and Methodologies
147(22)
7.1 Introduction: Thermal Fundamentals and Challenges
147(4)
7.1.1 Heat Generation
148(1)
7.1.2 Heat Transfer
148(3)
7.1.3 State of the Art: Thermal Modeling
151(1)
7.2 3D Thermal Modeling
151(3)
7.3 Heat Transfer in 3D-ICs
154(2)
7.4 3D Tree-Based FPGA Thermal Analysis Model
156(5)
7.4.1 3D Thermal Aware Design Techniques
157(2)
7.4.2 TSV Aware Thermal Control
159(2)
7.5 3D FPGA Thermal Modeling: Capabilities
161(1)
7.6 3D FPGA Thermal Modeling: Simulation Results
162(4)
7.7 Summary
166(3)
References
167(2)
8 Physical Design and Implementation of 3D Tree-Based FPGAs
169(32)
8.1 Introduction
169(1)
8.2 3D Tree-Based FPGA Design Requirements
170(4)
8.2.1 Why Tree-Based Interconnect and Not Mesh
170(3)
8.2.2 3D Tree-Based Interconnect: A Requirement for High Logic Density
173(1)
8.3 2D Physical Design of Tree-Based FPGA
174(4)
8.3.1 Method 1: Coalesce Scalable Tree-Based 2D Layout Design
175(1)
8.3.2 Method 2: Level-Wise 2D Tree Layout Design
176(2)
8.4 Sub-path Timing Characterization
178(3)
8.5 3D Design Methodologies
181(6)
8.5.1 Vertical Partitioning
183(1)
8.5.2 Horizontal Partitioning
184(2)
8.5.3 Through Silicon via (TSV) Modeling
186(1)
8.6 3D Tree-Based FPGA Physical Design Flow
187(9)
8.6.1 3D Stacking Methodologies
189(2)
8.6.2 3D FPGA Placement and Route
191(3)
8.6.3 3D Design Sign Off Analysis
194(2)
8.7 3D Timing Analysis
196(2)
8.8 Summary
198(3)
References
198(3)
9 Three-Dimensional FPGAs: Future Lines of Research
201(10)
9.1 Introduction: 3D FPGA Research
201(1)
9.2 Tree-Based Interconnect Partitioning
202(1)
9.2.1 Vertical Partitioning
202(1)
9.2.2 Horizontal Partitioning
203(1)
9.3 3D Physical Design Methodology and CAD Support
203(2)
9.3.1 Interconnect Optimization Model
204(1)
9.3.2 3D FPGA Architecture Exploration Tools and Technologies
204(1)
9.4 Directions for Future Work
205(6)
9.4.1 Technology Research
206(1)
9.4.2 Alternative Memory Technology
206(1)
9.4.3 Monolithic 3D-FPGA
207(1)
9.4.4 3D Hybrid FPGA (3D-HFPGA): CNT Based FPGA Interconnect
207(1)
9.4.5 Mesh-of-Tree-based Embedded FPGA
208(1)
9.4.6 3D FPGA CAD Tools
208(1)
References
208(3)
Appendix A FPGA CAD Tool: 3D Homogeneous Tree-Based FPGA Architecture and Design Space Exploration 211(4)
Appendix B FPGA CAD Tool: 3D Heterogeneous Tree-Based FPGA Exploration 215(6)
Appendix C FPGA CAD Tool: 3D MoT-Based FPGA Exploration 221(2)
Appendix D 3D Tree-Based FPGA Thermal Modeling 223