MONDAY, OCTOBER 26, 1999 |
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SESSION I - PLENARY |
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Interconnect Limits on Gigascale Integration (Keynote) |
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3 | (2) |
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Electronic Packaging For Microwave Multichip Modules (Keynote) |
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5 | (4) |
SESSION II - SYSTEM DESIGN ISSUES I |
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Challenges in the Packaging of an Eight Way Server (Invited) |
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9 | (2) |
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Physical Layer Design of a 1.6 GB/s DRAM Bus |
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11 | (4) |
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Implementation Considerations for RAMBUS™-based Systems |
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15 | (6) |
SESSION III - SYSTEM DESIGN ISSUES II |
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Noise Verification Across 3 Levels of Packaging Hierarchy for the IBM G5/G6 Mainframes |
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21 | (4) |
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Noise Measurements on Power4 Test Chip |
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25 | (4) |
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Half-Conductive Coupling for Chip-to-Chip Connections |
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29 | (4) |
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RF Interconnect for Multi-Gbit/sec Board-Level Clock Distribution |
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33 | (4) |
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Operating Frequency Trends for High Performance Off-Chip Buses |
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37 | (8) |
SESSION IV - ON CHIP INTERCONNECTIONS |
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On-Chip Wiring Design Challenges for GHz Operation (Invited) |
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45 | (4) |
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Reliability and Performance Tradeoffs in the Design of On-Chip Power Delivery and Interconnects (Invited) |
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49 | (4) |
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Impact of Cross-over Lines on Delay Time of Two Parallel Global Wires |
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53 | (4) |
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Asymptotically Zero Power Dissipation Gigahertz Clock Distribution Networks |
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57 | (6) |
SESSION V - MEASUREMENT |
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Picosecond Time-Domain Photoconductive Sampling Method For Measuring Guided and Free-Space Pulse Propagation |
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63 | (4) |
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Limitations Due to Systematic Phase Errors on the Extraction of Loss Tangent From Micronsized Transmission Line Test Structures |
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67 | (4) |
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Parameter Extraction for Circuit Models of Electronic Packages Without Optimization |
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71 | (4) |
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Electrical Characterization of S/390 MCM Packages from S-Parameter Measurements below 3 GHz |
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75 | (6) |
SESSION VI - MODELING I |
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Domain Decomposition Approach for Capacitance Computation of Non-orthogonal Interconnect Structures |
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81 | (4) |
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Improved Global Rational Approximation Macromodeling Alogrithm for Transient Simulation of Interconnects |
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85 | (4) |
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Application of Subspace Projection Approaches for Reduced-Order Modeling of Electromagnetic Systems |
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89 | (6) |
SESSION VII - OPEN FORUM (POSTERS) |
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Numerical Analysis of Surface Waves on a Grounded Dielectric Plane Using the Finite Difference Time Domain Method |
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95 | (4) |
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Modeling the Effects of Non-Linear Materials in De-Coupling Components of Digital Systems |
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99 | (4) |
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Power Distribution Modeling and Decoupling of Multilayer Printed Circuit Board |
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103 | (4) |
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Electrical Performance of Buried Capacitors in Multi-layered PCBs |
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107 | (4) |
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Precise Chip and Package 3D Capacitance Simulations of Realistic Interconnects Using a General Purpose FEM-Tool |
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111 | (4) |
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RF Characterization of Low Cost MCM-D Substrates, Manufactured on Large Area Panels |
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115 | (6) |
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Validation of Integrated Capacitor-Via-Planes Model |
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121 | (4) |
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High Performance Socket Characterization Technique for Microprocessors |
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125 | (4) |
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Achieving 800 MT/s Performance with PGA370 Socket |
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129 | (4) |
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An Accurate and Complete Frequency Dependent Transmission Line Characterization Using S-Parameter Measurements |
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133 | (4) |
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Transmission Link Radiation: Localized Defect Contribution |
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137 | (4) |
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Power Plane Decoupling Strategy for High Speed Processor Boards |
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141 | (6) |
TUESDAY, OCTOBER 27, 1999 |
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SESSION VIII - POWER DISTRIBUTION |
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Simultaneous Switching, Noise, and Reliability Analysis of VLSI Core Logic (Invited) |
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147 | (2) |
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Modeling and Transient Simulation of Planes in Electronic Packages for GHz Systems |
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149 | (4) |
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Accuracy Considerations of Power-Ground Plane Models |
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153 | (4) |
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Computation of the Frequency Response of Multiple Planes in Gigahertz Packages and Boards |
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157 | (6) |
SESSION IX - SSN |
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Simultaneous Switch Noise and Power Plane Bounce for CMOS Technology (Invited) |
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163 | (4) |
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Modeling of Simultaneous Switching Output by Equivalent Source Impedance |
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167 | (4) |
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Off-Chip Delta-I Noise Modeling and Measurement Methodology |
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171 | (4) |
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Design and Performance Evaluation of Chip Capacitors on Microprocessor Packaging |
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175 | (6) |
SESSION X - TRANSMISSION LINE MODELING |
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Characteristic Impedance of Microstrip on Silicon |
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181 | (4) |
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Equivalent Circuit Modeling of Single and Coupled On-Chip Interconnects on Lossy Silicon Substrate |
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185 | (4) |
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Enhanced Skin Effect for Partial Element Equivalent Circuit (PEEC) Models |
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189 | (4) |
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Study of Meander Line Delay in Circuit Boards |
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193 | (6) |
SESSION XI - EMISSIONS |
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Radiated Emission from Pin-fin Heat Sink Mounted on an EBGA Package |
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199 | (4) |
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Methods to Reduce Radiation from Split Ground Plane Structures |
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203 | (4) |
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Distributed Effects of a Gap in Power/Ground Planes |
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207 | (4) |
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A Novel Time Domain Algorithm for Field Excited Lossy Transmission Lines |
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211 | (6) |
WEDNESDAY, OCTOBER 27, 1999 |
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SESSION XII - MICROWAVE/RF PACKAGING I |
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An Integrated Environment for the Simulation of Electrical, Thermal and Electromagnetic Interactions in High-Performance Integrated Circuits (Invited) |
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217 | (4) |
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Toward a Novel Planar Circuit Compatible Silicon Micromachined Waveguide |
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221 | (4) |
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77GHz Band Surface Mountable Ceramic Package |
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225 | (6) |
SESSION XIII - MICROWA VE/RF PACKAGING II |
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Design Rule Development for Microwave Flip Chip Applications |
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231 | (4) |
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High-Performance Silicon MMIC Interconnect for Millimeter Wave Wireless Communication |
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235 | (4) |
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Simulation of Embedded RF Circuits Using Macromodels and Synthesized Equivalent Circuits |
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239 | (6) |
SESSION XIV - MODELING II |
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On the Chicken-and-Egg Problem of Determining the Effect of Crosstalk on Delay In Integrated Circuits (Invited) |
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245 | (4) |
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Laguerre-SVD Reduced Order Modeling |
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249 | (4) |
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Latency Insertion Method for the Fast Simulation of Interconnection Networks |
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253 | (4) |
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A Fast Simulation Method for Single and Coupled Lossy Lines with Frequency-Dependent Parameters Based on Triangle Impulse Responses |
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257 | (4) |
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Efficient and Accurate Extraction of Frequency-Dependent Resistance and Inductance Parameters of Interconnects |
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261 | (4) |
Author Index |
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265 | |