| SESSION I--SYSTEM DESIGN ISSUES I |
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Reaching the Limits of CMOS Technology--(Keynote) |
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3 | (1) |
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Electrical Performance of Chip-On-Chip Modules |
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4 | (4) |
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Modeling, Simulation, and Design Methodology of The Interconnect Packaging of an Ultra-High Speed Source Synchronous Bus |
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8 | (7) |
| SESSION II--SYSTEM DESIGN ISSUES II |
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First Level Package Design Considerations for the IBM's S/390 G5 Server--(Invited) |
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15 | (2) |
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Bus Pumping at GBIT/S Data Rate on MCM |
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17 | (4) |
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Determination of the Optimal Signal/Ground Configuration of A Multi-Pins Connector for Minimal Crosstalk |
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21 | (6) |
| SESSION III--ON-CHIP INTERCONNECTIONS |
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Design Methodology for On-Chip Interconnects |
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27 | (4) |
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Signal Propagation on Seamless High Off-Chip Connectivity (SHOCC) Interconnects |
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31 | (4) |
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Frequency-dependent Crosstalk Modeling for On-chip Interconnections |
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35 | (4) |
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Flip-Chip Power Distribution |
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39 | (6) |
| SESSION IV--MEASUREMENT I |
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National Institute of Standards and Technology Programs in Electrical Measurements for Electronic Interconnections--(Invited) |
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45 | (5) |
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Inductance Measurement of Lead-Frame Packages |
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50 | (4) |
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High Frequency Limitations of the JEDEC 123 Guideline |
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54 | (7) |
| SESSION V--MEASUREMENTS II |
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Electrical Characterization of Ball Grid Array Packages from S-parameter Measurements below 500MHz |
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61 | (4) |
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On-chip Capacitor Measurement for High Performance Microprocessor |
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65 | (4) |
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Characterization of Frequency Dependent Dielectric Packaging Media Using Differential and Multiple-Reflection Techniques on a Precision Stripline Test Structure |
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69 | (4) |
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PLL Phase Error and Power Supply Noise |
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73 | (6) |
| SESSION VI--MIXED SIGNAL/OPTICAL PACKAGING DESIGN |
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A Novel High Isolation Interconnect for Broadband Mixed Signal Silicon MMICs |
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79 | (4) |
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Investigations of Multi-Layer Ceramic-Based MCM Technology |
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83 | (4) |
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Modeling of Free Space Holographic Optical Link for Board Level Interconnect |
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87 | (6) |
| SESSION VII--OPEN FORUM (POSTERS) |
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Temperature Stable Thermoplastic Microwave Materials and Copper Laminates |
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93 | (4) |
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Considerations of Characterizing Standard SMT Packages for RFIC Applications |
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97 | (4) |
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A Novel Electrical Performance Analysis for Leaded Packages |
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101 | (4) |
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Simulation and Evaluation of Ground Bounce Induced Crosstalk in a Mixed Logic Ball Grid Array Substrate Design |
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105 | (4) |
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A Custom Package Autoprober |
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109 | (4) |
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GaAs Multichip Packaging using the Selectively Oxidized Porous Silicon (SOPS) Substrate |
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113 | (3) |
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Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card |
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116 | (4) |
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Transient and Crosstalk Analysis of Interconnection Lines for Single Level Integrated Packaging Modules |
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120 | (4) |
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Scaling Analysis of Interconnectivity and Crosstalk in VLSI Circuits |
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124 | (4) |
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Skin Effects Models for Transmission Line Structures using Generic SPICE Circuit Simulators |
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128 | (4) |
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Evaluation and Optimization of MCM-BGA Packages |
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132 | (4) |
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Full-Wave Electromagnetic Modeling of Interconnects with Meshed Ground Planes |
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136 | (4) |
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Fast Method for the Prediction of the Capacitance of Via Through-holes |
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140 | (4) |
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Electromagnetic Interference Through Slots in Packaging Structures |
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144 | (4) |
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Multi Drop Net Topologies for MCM Off Chip Interconnection Lines |
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148 | (4) |
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High Frequency Equivalent Circuit Model of Via |
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152 | (7) |
| SESSION VIII--POWER DISTRIBUTION MODELING I |
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Modeling of Power Distribution Systems in PCs |
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159 | (4) |
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Accurate Power Supply and Ground Plane Pair Models |
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163 | (4) |
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Extraction of Equivalent Circuit Models of Package Power Supply Distribution Systems from Full Wave EM Field Simulations |
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167 | (4) |
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Incorporating Vertical Discontinuities in Power-Bus Modeling using a Mixed-Potential Integral Equation and Circuit Extraction Formulation |
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171 | (6) |
| SESSION IX--POWER DISTRIBUTION MODELING II |
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Effects of Power/Ground Via Distribution on the Power/Ground Performance of C4/BGA Packages |
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177 | (4) |
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Reducing Simultaneous Switching Noise and EMI on Ground/Power Planes by Dissipative Edge Termination |
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181 | (4) |
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Contribution of Resonance to Ground Bounce in Lossy Thin Film Plates |
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185 | (6) |
| SESSION X--SIMULTANEOUS SWITCHING NOISE |
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Characterization of Flip-Chip CMOS ASIC Simultanous Switching Noise on Multilayer Organic and Ceramic BGA/CGA Packages |
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191 | (4) |
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Norton Equivalent Modeling of Microprocessor Core Noise from Measurements |
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195 | (4) |
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Rejection of SSN Coupling in Multilayer PCB Using a Conductive Layer |
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199 | (6) |
| SESSION XI--POWER SUPPLY DECOUPLING |
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Modeling and Simulation of Thin Film Decoupling Capacitors |
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205 | (4) |
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Power Decoupling with Integral Capacitors and Area Array Connections |
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209 | (4) |
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ESR and ESL of Ceramic Capacitor Applied to Decoupling Applications |
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213 | (6) |
| SESSION XII--SILICON SUBSTRATE MODELING |
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Analytic Modeling of Monolithic Inductors on Semiconductor Substrates |
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219 | (4) |
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Simple Formulas to Calculate the Line Parameters of Interconnects on Conducting Substrates |
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223 | (4) |
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CAD-Oriented Equivalent Circuit Modeling of On-Chip Interconnects in CMOS Technology |
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227 | (6) |
| SESSION XIII--MICROWAVE PACKAGING I |
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Microwave & Millimeter Wave Ball Grid Array (BGA) Packages-(Invited) |
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233 | (4) |
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Electrical Modeling of a BGA Package for Microwave Applications--A Layer by Layer Approach |
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237 | (4) |
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Full Wave Analysis and Development of Circuit Models for Flip Chip Interconnects |
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241 | (6) |
| SESSION XIV--MICROWAVE PACKAGING II |
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Micromachined Silicon Conformal Packaging for Millimeter Wave System Applications--(Invited) |
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247 | (1) |
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A Monolithic Spiral Transmission-Line Balun |
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248 | (4) |
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Novel Microstrip-to-Stripline Transitions for Leakage Suppression in Multilayer Microwave Circuits |
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252 | (7) |
| SESSION XV--MODELING TECHNIQUES |
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The Application of the TLM Method to the Simulation of High-Speed and High-Complexity Electronic Systems--(Invited) |
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259 | (5) |
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Numerical Modeling of Packaging Effects Using the Finite-Difference Time-Domain Technique--(Invited) |
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264 | (3) |
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Canonical Package Problem Solved Using Six Different Codes |
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267 | (6) |
| SESSION XVI--ACCELERATED MODELING/SIMULATION I |
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Improved Integral Formulations for Fast 3-D Method-of-Moments Solvers |
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273 | (4) |
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Efficient Computation of Interconnect Capacitances Using the Domain Decomposition Approach |
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277 | (4) |
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Recent Improvements for Fast Inductance Extraction and Simulation |
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281 | (6) |
| SESSION XVII--ACCELERATED MODELING/SIMULATION II |
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Model Reduction for PEEC Models Including Retardation |
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287 | (4) |
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Passive Model Order Reduction of Multiconductor Interconnects |
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291 | (4) |
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Efficient Simulation of High-Speed Distributed Interconneccts Using Krylov-Subspace Techniques |
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295 | (4) |
| Author Index |
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299 | |
