| About the Authors |
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xv | |
| About the Technical Reviewers |
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xvii | |
| Acknowledgments |
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xix | |
| Foreword |
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xxi | |
| Introduction |
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xxiii | |
| Chapter 1 Introduction |
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1 | (12) |
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What Is Embedded Firmware? |
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1 | (2) |
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3 | (1) |
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What Do Firmware Engineers Do? |
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3 | (1) |
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Firmware Preparation for New Hardware |
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3 | (1) |
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4 | (2) |
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6 | (1) |
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The Intel® Firmware Support Package |
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7 | (1) |
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The Uniqueness of Embedded Firmware |
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8 | (1) |
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The Choice of Firmware Stacks |
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9 | (1) |
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Welcome to the Era of the Internet of Things |
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9 | (1) |
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Technical Coverage in This Book |
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10 | (1) |
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10 | (3) |
| Chapter 2 Firmware Stacks for Embedded Systems |
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13 | (12) |
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Is a One-Size-Fits-All Solution Possible? |
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15 | (1) |
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16 | (1) |
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Real-Time Operating System (RTOS) |
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16 | (1) |
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17 | (1) |
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Implementations of the UEFI Framework |
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18 | (1) |
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Open Source Firmware Stacks |
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18 | (1) |
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Proprietary Firmware Stacks |
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19 | (1) |
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20 | (4) |
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The Advantages of Outsourcing |
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22 | (1) |
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The Disadvantages of Outsourcing |
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22 | (1) |
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23 | (1) |
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24 | (1) |
| Chapter 3 Intel® Firmware Support Package (Intel® FSP) |
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25 | (30) |
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27 | (1) |
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28 | (3) |
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31 | (2) |
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33 | (3) |
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Locating the Entries of Intel FSP |
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36 | (3) |
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The Hard Way to Find Intel FSP APIs: Use Data Structure |
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36 | (2) |
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The Easy Way to Find FSP APIs: Use Hard-Coded Constants |
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38 | (1) |
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Programming Interface: The APIs of Intel FSP |
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39 | (5) |
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39 | (3) |
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42 | (1) |
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43 | (1) |
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44 | (3) |
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45 | (1) |
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Temporary Memory Data HOB |
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45 | (1) |
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46 | (1) |
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Sample Code for Parsing HOBs |
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46 | (1) |
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Customization of Intel FSP |
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47 | (2) |
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49 | (3) |
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52 | (1) |
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53 | (1) |
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53 | (1) |
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53 | (1) |
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What Is Coming in the Following
Chapters |
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54 | (1) |
| Chapter 4 Building coreboot with Intel FSP |
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55 | (42) |
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The Introduction of coreboot |
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55 | (1) |
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The Philosophy of coreboot |
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56 | (1) |
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57 | (4) |
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57 | (1) |
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57 | (1) |
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58 | (1) |
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59 | (1) |
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2008 LinuxBIOS Renamed "coreboot" |
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59 | (1) |
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59 | (1) |
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59 | (1) |
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60 | (1) |
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Prerequisites for Working with coreboot |
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61 | (3) |
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61 | (1) |
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61 | (1) |
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62 | (1) |
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coreboot Sign-off Procedure |
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63 | (1) |
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Working with the coreboot Community |
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64 | (1) |
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64 | (1) |
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65 | (1) |
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Nonsource Binaries in coreboot |
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65 | (1) |
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A Hands-on Example: Building coreboot for the MinnowBoard MAX Mainboard |
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65 | (11) |
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66 | (1) |
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67 | (1) |
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67 | (1) |
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67 | (1) |
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Downloading the coreboot Source |
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68 | (1) |
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68 | (1) |
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69 | (1) |
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Creating a coreboot Development Branch |
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69 | (1) |
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70 | (5) |
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75 | (1) |
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76 | (4) |
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76 | (1) |
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77 | (1) |
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77 | (2) |
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79 | (1) |
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79 | (1) |
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Boot Flow Using Intel FSP |
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80 | (2) |
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Reset Vector and Bootblock |
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80 | (1) |
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80 | (1) |
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81 | (1) |
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82 | (1) |
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82 | (12) |
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82 | (5) |
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coreboot Hardwaremain State Machine |
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87 | (1) |
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88 | (2) |
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90 | (4) |
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coreboot Troubleshooting and Debugging |
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94 | (1) |
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94 | (1) |
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95 | (1) |
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95 | (1) |
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95 | (2) |
| Chapter 5 Chrome book Firmware Internals |
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97 | (24) |
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About Chrome book and Chrome OS |
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97 | (1) |
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Chrome OS Firmware Overview |
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98 | (1) |
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Chrome OS Security Philosophy |
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98 | (1) |
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Chrome OS Security Guiding Principles |
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98 | (1) |
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99 | (1) |
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99 | (1) |
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99 | (1) |
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99 | (1) |
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100 | (1) |
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100 | (1) |
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101 | (1) |
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101 | (1) |
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101 | (3) |
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102 | (1) |
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103 | (1) |
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Verified Boot and Kernel Security |
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104 | (1) |
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Chrome OS Firmware Boot Log |
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104 | (1) |
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105 | (1) |
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Chrome OS Firmware Event Log |
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105 | (1) |
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Google SMI Linux Kernel Driver |
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106 | (1) |
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Chrome OS Extensions to the Firmware Image |
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106 | (7) |
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106 | (3) |
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Google Binary Block (GBB) |
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109 | (3) |
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112 | (1) |
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112 | (1) |
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Chrome OS Firmware Update |
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113 | (1) |
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113 | (5) |
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114 | (1) |
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114 | (1) |
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115 | (2) |
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117 | (1) |
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Google Embedded Controller |
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118 | (2) |
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118 | (1) |
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119 | (1) |
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119 | (1) |
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119 | (1) |
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Other Peripheral Controls |
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119 | (1) |
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119 | (1) |
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120 | (1) |
| Chapter 6 Intel FSP and UEFI Integration |
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121 | (24) |
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121 | (4) |
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123 | (2) |
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125 | (1) |
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125 | (1) |
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125 | (1) |
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126 | (2) |
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Generic FSP Wrapper Boot Flow |
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128 | (1) |
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128 | (4) |
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128 | (1) |
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Memory Layout for a Normal Boot Flow |
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129 | (1) |
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FSP Normal Boot Data Structure |
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130 | (2) |
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132 | (2) |
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132 | (1) |
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132 | (1) |
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133 | (1) |
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134 | (4) |
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134 | (1) |
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Capsule Update Memory Layout |
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135 | (1) |
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136 | (1) |
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FSP Recovery Memory Layout |
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137 | (1) |
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coreboot Payload Based upon EDK II |
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138 | (2) |
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Building Minnow and MinnowMax with FSP |
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140 | (3) |
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143 | (2) |
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| Chapter 7 Building Firmware for Quark Processors |
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145 | (28) |
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145 | (2) |
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History of Implementations and Specifications |
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146 | (1) |
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Introduction to EDK II Building Blocks |
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147 | (13) |
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147 | (2) |
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149 | (1) |
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PCD: Platform Configuration Database |
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150 | (3) |
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DEC: Platform Declaration File |
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153 | (2) |
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DSC: Platform Description File |
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155 | (1) |
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FDF: Flash Description File |
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156 | (1) |
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Build: The EDK II Build Command |
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156 | (2) |
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158 | (1) |
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159 | (1) |
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Introduction to the EDK II Subset |
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160 | (1) |
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160 | (11) |
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ROM Flash Image Size Optimization |
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161 | (7) |
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RAM Footprint Optimization |
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168 | (3) |
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171 | (2) |
| Chapter 8 Putting It All Together |
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173 | (6) |
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174 | (1) |
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Intel FSP and Open Source Philosophy |
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175 | (1) |
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Customization and Production of Intel FSP |
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176 | (1) |
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It Is a Community Effort After All |
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176 | (3) |
| Appendix A: Sample Boot Setting File (BSF) |
|
179 | (12) |
| Index |
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191 | |
