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Embedded SoPC Design with Nios II Processor and VHDL Examples [Kõva köide]

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(Cleveland State University)
  • Formaat: Hardback, 736 pages, kõrgus x laius x paksus: 259x185x43 mm, kaal: 1415 g
  • Ilmumisaeg: 21-Oct-2011
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 111800888X
  • ISBN-13: 9781118008881
Teised raamatud teemal:
Embedded SoPC Design with Nios II Processor and VHDL ExamplesSuurem pilt
  • Formaat: Hardback, 736 pages, kõrgus x laius x paksus: 259x185x43 mm, kaal: 1415 g
  • Ilmumisaeg: 21-Oct-2011
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 111800888X
  • ISBN-13: 9781118008881
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781118008881.html
Märksõnad:
The book is divided into four major parts. Part I covers HDL constructs and synthesis of basic digital circuits. Part II provides an overview of embedded software development with the emphasis on low-level I/O access and drivers. Part III demonstrates the design and development of hardware and software for several complex I/O peripherals, including PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card. Part IV provides three case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelbrot set fractal circuit, and an audio synthesizer based on DDFS (direct digital frequency synthesis) methodology.

The book utilizes FPGA devices, Nios II soft-core processor, and development platform from Altera Co., which is one of the two main FPGA manufactures. Altera has a generous university program that provides free software and discounted prototyping boards for educational institutions (details at http://www.altera.com/university). The two main educational prototyping boards are known as DE1 ($99) and DE2 ($269). All experiments can be implemented and tested with these boards. A board combined with this book becomes a “turn-key” solution for the SoPC design experiments and projects. Most HDL and C codes in the book are device independent and can be adapted by other prototyping boards as long as a board has similar I/O configuration.

Preface xxv
Acknowledgments xxxi
1 Overview of Embedded System
1(10)
1.1 Introduction
1(2)
1.1.1 Definition of an embedded system
1(1)
1.1.2 Example systems
2(1)
1.2 System design requirements
3(1)
1.3 Embedded SoPC systems
4(4)
1.3.1 Basic development flow
5(3)
1.4 Book organization
8(1)
1.5 Bibliographic notes
8(3)
PART I BASIC DIGITAL CIRCUITS DEVELOPMENT
2 Gate-level Combinational Circuit
11(10)
2.1 Overview of VHDL
11(1)
2.2 General description
12(4)
2.2.1 Basic lexical rules
13(1)
2.2.2 Library and package
13(1)
2.2.3 Entity declaration
13(1)
2.2.4 Data type and operators
13(1)
2.2.5 Architecture body
14(1)
2.2.6 Code of a 2-bit comparator
15(1)
2.3 Structural description
16(2)
2.4 Testbench
18(1)
2.5 Bibliographic notes
19(1)
2.6 Suggested experiments
20(1)
2.6.1 Code for gate-level greater-than circuit
20(1)
2.6.2 Code for gate-level binary decoder
20(1)
3 Overview of FPGA and EDA Software
21(28)
3.1 FPGA
21(5)
3.1.1 Overview of a general FPGA device
21(2)
3.1.2 Overview of the Altera Cyclone II devices
23(3)
3.2 Overview of the Altera DE1 and DE2 boards
26(1)
3.3 Development flow
26(3)
3.4 Overview of Quartus II
29(2)
3.5 Short tutorial of Quartus II
31(11)
3.5.1 Create the design project
32(5)
3.5.2 Create a testbench and perform the RTL simulation
37(1)
3.5.3 Compile the project
37(2)
3.5.4 Perform timing analysis
39(1)
3.5.5 Program the FPGA device
39(3)
3.6 Short tutorial on the ModelSim HDL simulator
42(5)
3.7 Bibliographic notes
47(1)
3.8 Suggested experiments
47(2)
3.8.1 Gate-level greater-than circuit
47(1)
3.8.2 Gate-level binary decoder
47(2)
4 RT-level Combinational Circuit
49(34)
4.1 RT-level components
49(6)
4.1.1 Relational operators
51(1)
4.1.2 Arithmetic operators
51(1)
4.1.3 Other synthesis-related VHDL constructs
52(2)
4.1.4 Summary
54(1)
4.2 Routing circuit with concurrent assignment statements
55(5)
4.2.1 Conditional signal assignment statement
55(3)
4.2.2 Selected signal assignment statement
58(2)
4.3 Modeling with a process
60(1)
4.3.1 Process
60(1)
4.3.2 Sequential signal assignment statement
60(1)
4.4 Routing circuit with if and case statements
61(6)
4.4.1 If statement
61(2)
4.4.2 Case statement
63(1)
4.4.3 Comparison to concurrent statements
64(2)
4.4.4 Unintended memory
66(1)
4.5 Constants and generics
67(2)
4.5.1 Constants
67(1)
4.5.2 Generics
68(1)
4.6 Design examples
69(11)
4.6.1 Hexadecimal digit to seven-segment LED decoder
69(3)
4.6.2 Sign-magnitude adder
72(2)
4.6.3 Barrel shifter
74(1)
4.6.4 Simplified floating-point adder
75(5)
4.7 Bibliographic notes
80(1)
4.8 Suggested experiments
80(3)
4.8.1 Multi-function barrel shifter
80(1)
4.8.2 Dual-priority encoder
81(1)
4.8.3 BCD incrementor
81(1)
4.8.4 Floating-point greater-than circuit
81(1)
4.8.5 Floating-point and signed integer conversion circuit
81(1)
4.8.6 Enhanced floating-point adder
82(1)
5 Regular Sequential Circuit
83(44)
5.1 Introduction
83(2)
5.1.1 D FF and register
84(1)
5.1.2 Synchronous system
84(1)
5.1.3 Code development
85(1)
5.2 HDL code of the basic storage elements
85(8)
5.2.1 D FF
86(3)
5.2.2 Register
89(1)
5.2.3 Register file
89(4)
5.2.4 SRAM
93(1)
5.3 Simple design examples
93(5)
5.3.1 Shift register
94(1)
5.3.2 Binary counter and variant
95(3)
5.4 Testbench for sequential circuits
98(3)
5.5 Timing analysis
101(3)
5.5.1 Timing parameters
101(2)
5.5.2 Timing considerations in Quartus II
103(1)
5.6 Case study
104(9)
5.6.1 Stopwatch
104(4)
5.6.2 FIFO buffer
108(5)
5.7 Cyclone II device embedded memory module
113(9)
5.7.1 Overview of memory options of DE1 board
113(1)
5.7.2 Overview of embedded M4K module
114(1)
5.7.3 Methods to incorporate embedded memory module
114(2)
5.7.4 HDL module to infer synchronous single-port RAM
116(1)
5.7.5 HDL module to infer synchronous simple dual-port RAM
117(2)
5.7.6 HDL module to infer synchronous true dual-port RAM
119(1)
5.7.7 HDL module to infer synchronous ROM
120(1)
5.7.8 FIFO buffer revisited
121(1)
5.8 Bibliographic notes
122(1)
5.9 Suggested experiments
122(5)
5.9.1 Programmable square wave generator
122(1)
5.9.2 Pulse width modulation circuit
122(1)
5.9.3 Rotating square circuit
123(1)
5.9.4 Heartbeat circuit
123(1)
5.9.5 Rotating LED banner circuit
123(1)
5.9.6 Enhanced stopwatch
123(1)
5.9.7 FIFO with data width conversion
124(1)
5.9.8 Stack
124(1)
5.9.9 ROM-based sign-magnitude adder
124(1)
5.9.10 ROM-based temperature conversion
124(3)
6 FSM
127(20)
6.1 Introduction
127(4)
6.1.1 Mealy and Moore outputs
128(1)
6.1.2 FSM representation
128(3)
6.2 FSM code development
131(3)
6.3 Design examples
134(10)
6.3.1 Rising-edge detector
134(4)
6.3.2 Debouncing circuit
138(4)
6.3.3 Testing circuit
142(2)
6.4 Bibliographic notes
144(1)
6.5 Suggested experiments
144(3)
6.5.1 Dual-edge detector
144(1)
6.5.2 Alternative debouncing circuit
144(1)
6.5.3 Parking lot occupancy counter
144(3)
7 FSMD
147(34)
7.1 Introduction
147(6)
7.1.1 Single RT operation
148(1)
7.1.2 ASMD chart
148(2)
7.1.3 Decision box with a register
150(3)
7.2 Code development of an FSMD
153(6)
7.2.1 Debouncing circuit based on RT methodology
153(1)
7.2.2 Code with explicit data path components
153(3)
7.2.3 Code with implicit data path components
156(1)
7.2.4 Comparison
157(2)
7.3 Design examples
159(15)
7.3.1 Fibonacci number circuit
159(3)
7.3.2 Division circuit
162(3)
7.3.3 Binary-to-BCD conversion circuit
165(3)
7.3.4 Period counter
168(3)
7.3.5 Accurate low-frequency counter
171(3)
7.4 Bibliographic notes
174(1)
7.5 Suggested experiments
174(7)
7.5.1 Alternative debouncing circuit
174(1)
7.5.2 BCD-to-binary conversion circuit
175(1)
7.5.3 Fibonacci circuit with BCD I/O: design approach 1
175(1)
7.5.4 Fibonacci circuit with BCD I/O: design approach 2
175(1)
7.5.5 Auto-scaled low-frequency counter
176(1)
7.5.6 Reaction timer
176(1)
7.5.7 Babbage difference engine emulation circuit
177(4)
PART II BASIC NIOS II SOFTWARE DEVELOPMENT
8 Nios II Processor Overview
181(8)
8.1 Introduction
181(2)
8.2 Register file and ALU
183(1)
8.2.1 Register file
183(1)
8.2.2 ALU
184(1)
8.3 Memory and I/O organization
184(3)
8.3.1 Nios II memory interface
184(1)
8.3.2 Overview of memory hierarchy
184(1)
8.3.3 Virtual memory
184(1)
8.3.4 Memory protection
185(1)
8.3.5 Cache memory
186(1)
8.3.6 Tightly coupled memory
186(1)
8.3.7 I/O organization
186(1)
8.3.8 Interconnect structure
187(1)
8.4 Exception and interrupt handler
187(1)
8.5 JTAG debug module
187(1)
8.6 Bibliographic notes
187(1)
8.7 Suggested projects
188(1)
8.7.1 Comparison of Nios II and MIPS
188(1)
9 Nios II System Derivation and Low-Level Access
189(28)
9.1 Development flow revisited
189(3)
9.1.1 Hardware development
189(2)
9.1.2 Software development
191(1)
9.1.3 Flashing-LED system
191(1)
9.2 Nios II hardware generation tutorial
192(8)
9.2.1 Create a hardware project in Quartus II
192(1)
9.2.2 Create a Nios II system and generate HDL codes
192(6)
9.2.3 Create a top-level HDL file that instantiates the Nios II system
198(1)
9.2.4 Compiling and programming
199(1)
9.3 Nios II SBT GUI tutorial
200(4)
9.3.1 Create BSP library
200(1)
9.3.2 Configure the BSP using BSP Editor
200(2)
9.3.3 Create user application directory and add application files
202(1)
9.3.4 Build and run software
203(1)
9.3.5 Check code size
204(1)
9.4 System id core for hardware-software consistency
204(2)
9.5 Direct low-level I/O access
206(2)
9.5.1 Review of C pointer
206(1)
9.5.2 C pointer for I/O register
207(1)
9.6 Robust low-level I/O access
208(2)
9.6.1 system.h
208(1)
9.6.2 alt_types.h
209(1)
9.6.3 io.h
209(1)
9.7 Some C techniques for low-level I/O operations
210(1)
9.7.1 Bit manipulation
210(1)
9.7.2 Packing and unpacking
210(1)
9.8 Software development
211(2)
9.8.1 Basic embedded program architecture
211(1)
9.8.2 Main program and task routines
212(1)
9.9 Bibliographic notes
213(1)
9.10 Suggested experiments
213(2)
9.10.1 Chasing LED circuit
213(1)
9.10.2 Collision LED circuit
214(1)
9.10.3 Pulse width modulation circuit
214(1)
9.10.4 Rotating square circuit
214(1)
9.10.5 Heartbeat circuit
214(1)
9.11 Complete program listing
215(2)
10 Predesigned Nios II I/O Peripherals
217(38)
10.1 Overviews
217(1)
10.2 PIO core
218(4)
10.2.1 Configuration
218(3)
10.2.2 Register map
221(1)
10.2.3 Visible register
222(1)
10.3 JTAG UART core
222(2)
10.3.1 Configuration
222(1)
10.3.2 Register map
223(1)
10.4 Internal timer core
224(2)
10.4.1 Configuration
224(1)
10.4.2 Register map
225(1)
10.5 Enhanced flashing-LED Nios II system
226(6)
10.5.1 SOPC design
226(4)
10.5.2 Top-level HDL file
230(2)
10.6 Software development of enhanced flashing-LED system
232(2)
10.6.1 Introduction to device driver
232(1)
10.6.2 Program structure of the enhanced flashing-LED system
233(1)
10.6.3 Main program
233(1)
10.6.4 Function naming convention
234(1)
10.7 Device driver routines
234(5)
10.7.1 Driver for PIO peripherals
234(3)
10.7.2 JTAG UART
237(1)
10.7.3 Timer
238(1)
10.8 Task routines
239(3)
10.8.1 The flashsys_init_v1() function
239(1)
10.8.2 The sw_get_command.v1() function
239(1)
10.8.3 The jtaguart_disp_msg_v1() function
240(1)
10.8.4 The sseg_disp_msg_v1() function
240(1)
10.8.5 The led_flash_v1() function
241(1)
10.9 Software construction and testing
242(1)
10.10 Bibliographic notes
242(1)
10.11 Suggested experiments
242(4)
10.11.1 "Uptime" feature in flashing-LED system
242(1)
10.11.2 Counting with different timer mode
243(1)
10.11.3 JTAG UART input
243(1)
10.11.4 Enhanced collision LED circuit
243(1)
10.11.5 Rotating LED banner circuit
244(1)
10.11.6 Enhanced stopwatch
244(1)
10.11.7 Parking lot occupancy counter
244(1)
10.11.8 Reaction timer with pushbutton switch control
244(1)
10.11.9 Reaction timer with keyboard control
244(1)
10.11.10 Communication with serial port
244(2)
10.12 Complete program listing
246(9)
11 Predesigned Nios II I/O Drivers and HAL API
255(22)
11.1 Overview of HAL
255(6)
11.1.1 Desktop-like and barebone embedded systems
256(1)
11.1.2 HAL paradigm
257(1)
11.1.3 Device classes
258(1)
11.1.4 HAL-compliant device drivers
259(1)
11.1.5 The _regs.h file
259(1)
11.1.6 HAL-based initialization sequence
260(1)
11.2 BSP
261(4)
11.2.1 Overview
261(1)
11.2.2 BSP file structure
261(1)
11.2.3 BSP configuration
261(4)
11.3 HAL-based flashing-LED program
265(5)
11.3.1 Functions using generic I/O devices
265(2)
11.3.2 Functions using non-generic I/O devices
267(1)
11.3.3 Initialization routine and main program
268(1)
11.3.4 Software construction and testing
269(1)
11.4 Device driver consideration
270(3)
11.4.1 I/O access methods
270(1)
11.4.2 Comparisons
271(1)
11.4.3 Device drivers in this book
272(1)
11.5 Bibliographic notes
273(1)
11.6 Suggested experiments
273(2)
11.6.1 "Uptime" feature in flashing-LED system
273(1)
11.6.2 Enhanced collision LED circuit
274(1)
11.6.3 Parking lot occupancy counter
274(1)
11.6.4 Reaction timer with keyboard control
274(1)
11.6.5 Digital alarm clock
274(1)
11.7 Complete program listing
275(2)
12 Interrupt and ISR
277(20)
12.1 Interrupt processing in the HAL framework
277(3)
12.1.1 Overview
278(1)
12.1.2 Interrupt controller of the Nios II processor
278(1)
12.1.3 Top-level exception handler
279(1)
12.1.4 Interrupt service routines
280(1)
12.2 Interrupt-based flashing-LED program
280(5)
12.2.1 Interrupt of timer core
281(1)
12.2.2 Driver of timer core
281(1)
12.2.3 ISR version 1
282(2)
12.2.4 ISR version 2
284(1)
12.3 Interrupt and scheduling
285(3)
12.3.1 Scheduling
285(2)
12.3.2 Performance
287(1)
12.4 Bibliographic notes
288(1)
12.5 Suggested experiments
288(2)
12.5.1 Flashing-LED system with pushbutton switch ISR
288(1)
12.5.2 ISR-driven flashing-LED system
288(1)
12.5.3 "Uptime" feature in flashing-LED system
289(1)
12.5.4 Reaction timer with keyboard control
289(1)
12.5.5 Digital alarm clock
289(1)
12.6 Complete program listing
290(7)
PART III CUSTOM I/O PERIPHERAL DEVELOPMENT
13 Custom I/O Peripheral with PIO Cores
297(8)
13.1 Introduction
297(1)
13.2 Integration of division circuit to a Nios II system
298(1)
13.2.1 PIO modules
298(1)
13.2.2 Integration
299(1)
13.3 Testing
299(3)
13.4 Suggested experiments
302(3)
13.4.1 Division core ISR
302(1)
13.4.2 Division core with eight-bit data
302(1)
13.4.3 Division core with 64-bit data
303(1)
13.4.4 Fibonacci number circuit
303(1)
13.4.5 Period counter
303(2)
14 Avalon Interconnect and SOPC Component
305(36)
14.1 Introduction
305(4)
14.2 Avalon MM interface
309(4)
14.2.1 Avalon MM slave interface signals
309(1)
14.2.2 Avalon MM slave interface properties
310(1)
14.2.3 Avalon MM slave timing
310(3)
14.3 System interconnect fabric for Avalon interface
313(2)
14.4 SOPC I/O component wrapping circuit
315(7)
14.4.1 Interface I/O buffer
315(3)
14.4.2 Memory alignment
318(1)
14.4.3 Output decoding from an Avalon MM master
318(2)
14.4.4 Input multiplexing to an Avalon MM master
320(1)
14.4.5 Practical consideration
321(1)
14.5 SOPC component construction tutorial
322(12)
14.5.1 Avalon interfaces
322(1)
14.5.2 Register map
323(1)
14.5.3 Wrapped division circuit
324(2)
14.5.4 SOPC component creation
326(7)
14.5.5 SOPC component instantiation
333(1)
14.6 Testing
334(4)
14.7 Bibliographic notes
338(1)
14.8 Suggested experiments
338(3)
14.8.1 Division core ISR
338(1)
14.8.2 Alternative buffering scheme for the division core
338(1)
14.8.3 Division core with eight-bit data
338(1)
14.8.4 Division core with 64-bit data
338(1)
14.8.5 Fibonacci number circuit
338(1)
14.8.6 Period counter
339(2)
15 SRAM and SDRAM Controllers
341(38)
15.1 Memory resources of DE1 board
341(1)
15.2 Brief overview of timing and clock management
342(3)
15.2.1 Clock distribution network
342(1)
15.2.2 Timing consideration of off-chip access
343(1)
15.2.3 PLL
344(1)
15.3 Overview of SRAM
345(5)
15.3.1 SRAM cell
345(1)
15.3.2 Basic organization
346(1)
15.3.3 Timing
347(2)
15.3.4 IS61LV25616AL SRAM device
349(1)
15.4 SRAM controller IP core
350(4)
15.4.1 Avalon interfaces
350(2)
15.4.2 Controller circuit
352(1)
15.4.3 SOPC component creation
353(1)
15.5 Overview of DRAM
354(5)
15.5.1 DRAM cell
354(2)
15.5.2 Basic DRAM organization
356(1)
15.5.3 DRAM timing
357(2)
15.6 Overview of SDRAM
359(4)
15.6.1 Basic SDRAM organization
359(1)
15.6.2 SDRAM timing
359(3)
15.6.3 ICSI IS42S16400 SDRAM device
362(1)
15.7 SDRAM controller and PLL
363(4)
15.7.1 Basic SDRAM controller
363(1)
15.7.2 SDRAM controller IP core
364(1)
15.7.3 SOPC PLL IP core
365(2)
15.8 Testing system
367(8)
15.8.1 Testing hardware configuration
367(5)
15.8.2 Testing software
372(3)
15.9 Bibliographic notes
375(1)
15.10 Suggested experiments
375(2)
15.10.1 SRAM controller without I/O register
375(1)
15.10.2 SRAM controller speed test
375(1)
15.10.3 SRAM controller with Avalon MM tristate interface
376(1)
15.10.4 SDRAM controller clock skew test
376(1)
15.10.5 Memory performance comparison
376(1)
15.10.6 Effect of cache memory
376(1)
15.10.7 SDRAM controller from scratch
376(1)
15.11 Complete program listing
377(2)
16 PS2 Keyboard and Mouse
379(52)
16.1 Introduction
379(1)
16.2 PS2 receiving subsystem
380(4)
16.2.1 PS2-device-to-host communication protocol
380(1)
16.2.2 Design and code
381(3)
16.3 PS2 transmitting subsystem
384(5)
16.3.1 Host-to-PS2-device communication protocol
384(1)
16.3.2 Design and code
385(4)
16.4 Complete PS2 system
389(2)
16.5 PS2 controller IP core development
391(3)
16.5.1 Avalon interfaces
391(1)
16.5.2 Register map
391(1)
16.5.3 Wrapped PS2 system
392(1)
16.5.4 SOPC component creation
393(1)
16.6 PS2 driver
394(2)
16.6.1 Register map
394(1)
16.6.2 Write routines
394(1)
16.6.3 Read routines
394(2)
16.7 Keyboard driver
396(5)
16.7.1 Overview of the scan code
396(1)
16.7.2 Interaction with host
397(1)
16.7.3 Driver routines
397(4)
16.8 Mouse driver
401(4)
16.8.1 Overview of PS2 mouse protocol
401(1)
16.8.2 Interaction with host
402(1)
16.8.3 Driver routines
403(2)
16.9 Test
405(2)
16.10 Use of book's custom IP cores
407(8)
16.10.1 IP core files
407(1)
16.10.2 Comprehensive Nios II testing system
408(7)
16.11 Bibliographic notes
415(1)
16.12 Suggested experiments
415(2)
16.12.1 PS2 receiving subsystem with watchdog timer
415(1)
16.12.2 Software receiving FIFO
415(1)
16.12.3 Software PS2 controller
415(1)
16.12.4 Keyboard-controlled LED flashing circuit
416(1)
16.12.5 Enhanced keyboard driver routine I
416(1)
16.12.6 Enhanced keyboard driver routine II
416(1)
16.12.7 Remote-mode mouse driver
416(1)
16.12.8 Scroll-wheel mouse driver
416(1)
16.13 Complete program listing
417(14)
17 VGA Controller
431(80)
17.1 Introduction
431(4)
17.1.1 Basic operation of a CRT
431(2)
17.1.2 VGA port of the DE1 board
433(1)
17.1.3 Video controller
434(1)
17.2 VGA synchronization
435(6)
17.2.1 Horizontal synchronization
436(1)
17.2.2 Vertical synchronization
437(1)
17.2.3 Timing calculation of VGA synchronization signals
438(1)
17.2.4 HDL implementation
438(3)
17.3 SRAM-based video RAM controller
441(9)
17.3.1 Overview of video memory
441(1)
17.3.2 Memory consideration of DE1 board
442(1)
17.3.3 Ad hoc SRAM controller
442(4)
17.3.4 HDL code
446(4)
17.4 Palette circuit
450(1)
17.5 Video controller IP core development
451(3)
17.5.1 Complete video controller
451(1)
17.5.2 Avalon interfaces
451(1)
17.5.3 Register map
451(1)
17.5.4 Wrapped video controller
452(2)
17.5.5 SOPC component creation
454(1)
17.6 Video driver
454(9)
17.6.1 Video memory access routines
454(2)
17.6.2 Geometrical model routine
456(1)
17.6.3 Bitmap processing routines
457(3)
17.6.4 Bit-mapped text routines
460(3)
17.7 Mouse processing routines
463(1)
17.8 Testing program
464(7)
17.8.1 Chart plotting routine
465(2)
17.8.2 General plotting functions
467(2)
17.8.3 Strip swapping routine
469(1)
17.8.4 Mouse demonstration routine
469(1)
17.8.5 Bit-mapped text routine
470(1)
17.9 Bitmap file processing
471(8)
17.9.1 BMP format overview
471(1)
17.9.2 Generation of BMP file
472(1)
17.9.3 Sprite-based design
472(1)
17.9.4 BMP file access
473(1)
17.9.5 Host-based file system
474(2)
17.9.6 Bitmap file retrieval routines
476(3)
17.10 Bibliographic notes
479(1)
17.11 Suggested experiments
480(2)
17.11.1 PLL-based VGA controller
480(1)
17.11.2 VGA controller with 16-bit memory configuration
480(1)
17.11.3 VGA controller with 3-bit color depth
480(1)
17.11.4 VGA controller with 1-bit color depth
480(1)
17.11.5 VGA controller with double buffering
480(1)
17.11.6 VGA controller with 320-by-240 resolution
480(1)
17.11.7 VGA controller with vertical mode operation
481(1)
17.11.8 Geometrical model functions
481(1)
17.11.9 Bitmap manipulation functions
481(1)
17.11.10 Simulated "Etch A Sketch" toy
481(1)
17.11.11 Palette lookup table circuit
481(1)
17.11.12 Virtual LED flashing system panel
481(1)
17.11.13 Virtual analog wall clock
482(1)
17.12 Suggested projects
482(2)
17.12.1 Configurable VGA controller
482(1)
17.12.2 VGA controller using system SDRAM
482(1)
17.12.3 Paint program
482(1)
17.12.4 Video game
483(1)
17.13 Complete program listing
484(27)
18 Audio Codec Controller
511(46)
18.1 Introduction
511(5)
18.1.1 Overview of codec
511(1)
18.1.2 Overview of WM8731 device
512(1)
18.1.3 Registers of WM8731 device
513(3)
18.2 I2C controller
516(8)
18.2.1 Overview of I2C interface
516(2)
18.2.2 HDL implementation
518(6)
18.3 Codec data access controller
524(3)
18.3.1 Overview of digital audio interface
524(1)
18.3.2 HDL implementation
525(2)
18.4 Audio codec controller IP core development
527(6)
18.4.1 Complete audio codec controller
527(2)
18.4.2 Avalon interfaces
529(1)
18.4.3 Register map
530(1)
18.4.4 Wrapped audio codec controller
531(2)
18.4.5 SOPC component creation
533(1)
18.5 Codec driver
533(3)
18.5.1 I2C command routines
533(1)
18.5.2 Data source select routine
534(1)
18.5.3 Device initialization routine
534(1)
18.5.4 Audio data access routines
535(1)
18.6 Testing program
536(3)
18.7 Audio file processing
539(4)
18.7.1 WAV format overview
539(1)
18.7.2 Audio format conversion program
540(1)
18.7.3 Audio data retrieval routine
541(2)
18.8 Bibliographic notes
543(1)
18.9 Suggested experiments
543(2)
18.9.1 Software I2C controller
543(1)
18.9.2 Hardware data access controller using master clocking mode
543(1)
18.9.3 Software data access controller using slave clocking mode
543(1)
18.9.4 Software data access controller using master clocking mode
543(1)
18.9.5 Configurable data access controller
544(1)
18.9.6 Voice recorder
544(1)
18.9.7 Real-time sinusoidal wave generator
544(1)
18.9.8 Real-time audio wave display
544(1)
18.9.9 Echo effect
544(1)
18.10 Suggested projects
545(1)
18.10.1 Full-fledged I2C controller
545(1)
18.10.2 Digital equalizer
545(1)
18.10.3 Digital audio oscilloscope
545(1)
18.11 Complete program listing
546(11)
19 SD Card Controller
557(62)
19.1 Overview of SD card
557(1)
19.2 SPI controller
558(4)
19.2.1 Overview of SPI interface
558(1)
19.2.2 HDL implementation
559(3)
19.3 SPI controller IP core development
562(2)
19.3.1 Avalon interfaces
562(1)
19.3.2 Register map
562(1)
19.3.3 Wrapped SPI controller
563(1)
19.3.4 SOPC component creation
564(1)
19.4 SD card protocol
564(5)
19.4.1 SD card command and response formats
564(2)
19.4.2 Initialization and identification process
566(1)
19.4.3 Data read and write process
567(2)
19.5 SPI and SD card driver
569(6)
19.5.1 SPI driver routines
569(1)
19.5.2 SD card driver routines
570(5)
19.6 File access
575(13)
19.6.1 Overview of FAT16 structure
576(5)
19.6.2 Read-only FAT16 file access driver routines
581(7)
19.7 Testing program
588(4)
19.8 Performance of SD card data transfer
592(1)
19.9 Bibliographic notes
593(1)
19.10 Suggested experiments
593(2)
19.10.1 SD card data transfer performance test
593(1)
19.10.2 Robust SD card driver routines
593(1)
19.10.3 Dedicated processor for SD card access
594(1)
19.10.4 Hardware-based SD card read and write operation
594(1)
19.10.5 SD card information retrieval
594(1)
19.10.6 MMC card support
594(1)
19.10.7 Multiple sector read and write operation
594(1)
19.10.8 SD card driver routines with CRC checking
595(1)
19.10.9 Digital music player
595(1)
19.10.10 Digital picture frame
595(1)
19.10.11 Additional FAT functionalities
595(1)
19.11 Suggested projects
595(1)
19.11.1 HAL API file access integration
595(1)
19.12 Complete program listing
596(23)
PART IV HARDWARE ACCELERATOR CASE STUDIES
20 GCD Accelerator
619(18)
20.1 Introduction
619(1)
20.2 Software implementation
620(1)
20.3 Hardware implementation
621(3)
20.3.1 ASMD chart
621(1)
20.3.2 HDL implementation
621(3)
20.4 Time measurement
624(1)
20.4.1 HAL time stamp driver
624(1)
20.4.2 Custom hardware counter
624(1)
20.5 GCD accelerator IP core development
625(2)
20.5.1 Avalon interfaces
625(1)
20.5.2 Register map
625(1)
20.5.3 Wrapped GCD accelerator
625(2)
20.6 Testing program
627(2)
20.6.1 GCD routines
627(2)
20.6.2 Main program
629(1)
20.7 Performance comparison
629(1)
20.8 Bibliographic notes
630(1)
20.9 Suggested experiments
630(2)
20.9.1 Performance with other processor configuration
630(1)
20.9.2 GCD accelerator with minimal size
630(1)
20.9.3 GCD accelerator with trailing zero circuit
631(1)
20.9.4 GCD accelerator with 64-bit data
631(1)
20.9.5 GCD accelerator with 128-bit data
631(1)
20.9.6 GCD by Euclid's algorithm
631(1)
20.10 Complete program listing
632(5)
21 Mandelbrot Set Fractal Accelerator
637(34)
21.1 Introduction
637(6)
21.1.1 Overview of the Mandelbrot set
639(1)
21.1.2 Determination of a Mandelbrot set point
639(1)
21.1.3 Coloring scheme
640(1)
21.1.4 Generation of a fractal image
641(2)
21.2 Fixed-point arithmetic
643(1)
21.3 Software implementation of calc_frac_point()
644(1)
21.4 Hardware implementation of calc_frac_point()
645(3)
21.4.1 ASMD chart
645(1)
21.4.2 HDL implementation
645(3)
21.5 Mandelbrot set fractal accelerator IP core development
648(2)
21.5.1 Avalon interface
648(1)
21.5.2 Register map
648(1)
21.5.3 Wrapped Mandelbrot set fractal accelerator
648(2)
21.6 Testing program
650(6)
21.6.1 Fractal graphic user interface
650(1)
21.6.2 Fractal hardware accelerator engine control routine
651(1)
21.6.3 Fractal drawing routine
652(1)
21.6.4 Text panel display routines
653(1)
21.6.5 Mouse processing routine
654(2)
21.6.6 Main program
656(1)
21.7 Discussion
656(1)
21.8 Bibliographic notes
657(1)
21.9 Suggested experiments
657(2)
21.9.1 Hardware accelerator with one multiplier
657(1)
21.9.2 Hardware accelerator with modified escape condition
658(1)
21.9.3 Hardware accelerator with Q4.12 format
658(1)
21.9.4 Hardware accelerator with multiple fractal engines
658(1)
21.9.5 "Burning-ship" fractal
658(1)
21.9.6 Enhanced testing program
658(1)
21.10 Suggested projects
659(1)
21.10.1 Floating-point hardware accelerator
659(1)
21.10.2 General fractal drawing platform
659(1)
21.11 Complete program listing
660(11)
22 Direct Digital Frequency Synthesis
671(26)
22.1 Introduction
671(1)
22.2 Design and implementation
671(6)
22.2.1 Direct synthesis of a digital waveform
672(1)
22.2.2 Direct synthesis of an unmodulated analog waveform
673(1)
22.2.3 Direct synthesis of a modulated analog waveform
674(1)
22.2.4 HDL implementation
674(3)
22.3 DDFS IP core development
677(3)
22.3.1 Avalon interface
677(1)
22.3.2 Register map
678(1)
22.3.3 Wrapped DDFS circuit
678(1)
22.3.4 Codec DAC integration
679(1)
22.4 DDFS driver
680(1)
22.4.1 Configuration routines
680(1)
22.4.2 Initialization routine
681(1)
22.5 Testing
681(6)
22.5.1 Overview of music notes and synthesis
682(1)
22.5.2 Testing program
683(4)
22.6 Bibliographic notes
687(1)
22.7 Suggested experiments
687(1)
22.7.1 Quadrature phase carrier generation
687(1)
22.7.2 Reduced-size phase-to-amplitude lookup table
687(1)
22.7.3 Synthetic music player
687(1)
22.7.4 Keyboard piano
688(1)
22.7.5 Keyboard recorder
688(1)
22.7.6 Hardware envelope generator
688(1)
22.7.7 Additive harmonic synthesis
688(1)
22.7.8 Sample-based synthesis
688(1)
22.8 Suggested projects
688(2)
22.8.1 Sound generator
688(1)
22.8.2 Function generator
689(1)
22.8.3 Full-fledged electric synthesizer
689(1)
22.9 Complete program listing
690(7)
References 697(4)
Topic Index 701
Dr. Pong P. Chu is an Associate Professor in the Department of Electrical and Computer Engineering at Cleveland State University in Ohio. He obtained a BS degree from National Chiao Tung University, Taiwan, and a PhD from Iowa State University. He has taught undergraduate- and graduate-level digital systems and computer architecture courses for more than a decade and has received instructional grants from the National Science Foundation and Cleveland State University.