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Embedded Systems: A Contemporary Design Tool 2nd edition [Kõva köide]

(University of Washington)
  • Formaat: Hardback, 1088 pages, kõrgus x laius x paksus: 259x211x46 mm, kaal: 2041 g
  • Ilmumisaeg: 02-May-2019
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 1119457505
  • ISBN-13: 9781119457503
Teised raamatud teemal:
Embedded Systems: A Contemporary Design Tool 2nd editionSuurem pilt
  • Formaat: Hardback, 1088 pages, kõrgus x laius x paksus: 259x211x46 mm, kaal: 2041 g
  • Ilmumisaeg: 02-May-2019
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 1119457505
  • ISBN-13: 9781119457503
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781119457503.html
Märksõnad:
Embedded Systems: A Contemporary Design Tool, Second Edition

Embedded systems are one of the foundational elements of todays evolving and growing computer technology. From operating our cars, managing our smart phones, cleaning our homes, or cooking our meals, the special computers we call embedded systems are quietly and unobtrusively making our lives easier, safer, and more connected. While working in increasingly challenging environments, embedded systems give us the ability to put increasing amounts of capability into ever-smaller and more powerful devices.

Embedded Systems: A Contemporary Design Tool, Second Edition introduces you to the theoretical hardware and software foundations of these systems and expands into the areas of signal integrity, system security, low power, and hardware-software co-design. The text builds upon earlier material to show you how to apply reliable, robust solutions to a wide range of applications operating in todays often challenging environments.

Taking the users problem and needs as your starting point, you will explore each of the key theoretical and practical issues to consider when designing an application in todays world. Author James Peckol walks you through the formal hardware and software development process covering:





Breaking the problem down into major functional blocks; Planning the digital and software architecture of the system; Utilizing the hardware and software co-design process; Designing the physical world interface to external analog and digital signals; Addressing security issues as an integral part of the design process; Managing signal integrity problems and reducing power demands in contemporary systems; Debugging and testing throughout the design and development cycle; Improving performance.

Stressing the importance of security, safety, and reliability in the design and development of embedded systems and providing a balanced treatment of both the hardware and the software aspects, Embedded Systems: A Contemporary Design Tool, Second Edition gives you the tools for creating embedded designs that solve contemporary real-world challenges.

Visit the book's website at: http://bcs.wiley.com/he-bcs/Books action=index&bcsId=11853&itemId=1119457505
About the Author xxxiii
Foreword xxxv
Preface xlix
Acknowledgment lix
About the Companion Website lxi
33 Hardware and Software Infrastructure
33 The Hardware Side -- Part 1: An Introduction
1(54)
33 Introduction
1(2)
33 The Hardware Side -- Getting Started
3(1)
33 The Core Level
3(5)
33 The Microprocessor
6(1)
33 The Microcomputer
7(1)
33 The Microcontroller
7(1)
33 The Digital Signal Processor
7(1)
33 Representing Information
8(1)
33 Word Size
9(1)
33 Understanding Numbers
9(4)
33 Resolution
10(1)
33 Propagation of Error
11(1)
33 Addition
11(1)
33 Multiplication
12(1)
33 Addresses
13(1)
33 Instructions
14(2)
33 Registers -- A First Look
16(2)
33 Embedded Systems -- An Instruction Set View
18(16)
33 Instruction Set -- Instruction Types
18(1)
33 Data Transfer Instructions
18(2)
33 Addressing Modes
20(6)
33 Execution How
26(1)
33 Sequential Flow
26(1)
33 Branch
27(1)
33 If-else Construct
28(1)
33 Loop
28(1)
33 Procedure or Function Call
29(3)
33 Arithmetic and Logic
32(2)
33 Embedded Systems -- A Register View
34(2)
33 The Basic Register
35(1)
33 Register Operations
35(1)
33 Write lo a Register
36(1)
33 Read from a Register
36(1)
33 Register Transfer Language
36(2)
33 Register View of a Microprocessor
38(7)
33 The Datapath
38(1)
33 Processor Control
39(1)
33 Fetch
39(1)
33 Decode
40(1)
33 Execute
40(1)
33 Next
41(4)
33 Summary
45(1)
33 Review Questions
45(1)
33 Thought Questions
46(1)
33 Problems
47(8)
33 The Hardware Side -- Part 2: Combinational Logic -- A Practical View
55(56)
33 Introduction
55(1)
33 A Look at Real-World Gates -- Part 1: Signal Levels
56(8)
33 Logic Levels
57(2)
33 A First Look Inside the Logic Gate
59(1)
33 Fan-In and Fan-Out
60(4)
33 A Look at Real-World Gates -- Part 2: Time
64(6)
33 Rise and Fall Times
65(1)
33 Propagation Delay
65(2)
33 Race Conditions and Hazards
67(1)
33 Static Hazard
67(2)
33 Dynamic Hazard
69(1)
33 A Look at Real-World Gates -- Part 3: Signal Behavior in the Real World -- the Legacy of Early Physicists
70(1)
33 Look For the Guilty -- A First Look at Signal Quality
71(10)
33 Resistors
71(1)
33 A Discrete Component First-Order Resistor Model
72(2)
33 Capacitors
74(2)
33 Discrete Component First-Order Capacitor Model
76(2)
33 Inductors
78(1)
33 Magnetic Field Lines -- The First Principle
78(1)
33 Magnetic Field Lines -- The Second Principle
79(1)
33 Magnetic Field Lines -- The Third Principle
80(1)
33 Inductance in Action
81(3)
33 Wires and Conductors
82(2)
33 Logic Circuit Models and Parasitic Components
84(7)
33 First-Order RC Circuit Model
84(2)
33 First-Order RL Circuit Model
86(1)
33 Second-Order Series RLC Circuit Model
87(2)
33 Tristate Drivers
89(1)
33 Open Gate Inputs
90(1)
33 Testing Combinational Circuits -- Introduction and Philosophy
91(1)
33 Modeling, Simulation, and Tools
92(1)
33 Structural Faults
93(6)
33 Stuck-at Faults
93(1)
33 Stuck-at-Zero Faults
94(1)
33 Stuck-at-One Faults
95(1)
33 Open Circuit Faults
96(1)
33 Bridging Faults
96(1)
33 Nonfeedback Bridge Faults
97(2)
33 Feedback Bridge Faults
99(1)
33 Functional Faults
99(2)
33 Hazards and Race Conditions
100(1)
33 Summary
101(1)
33 Review Questions
101(1)
33 Thought Questions
102(2)
33 Problems
104(7)
33 The Hardware Side -- Part 3: Storage Elements and Finite-State Machines -- A Practical View
111(54)
33 Introduction
111(1)
33 The Concepts of State and Time
112(1)
33 Time
112
33 State
112(1)
33 State Changes
113(1)
33 The State Diagram
113(1)
33 Finite-Stale Machines -- A Theoretical Model
114(2)
33 Designing Finite-State Machines -- Part 1: Registers
116(8)
33 Storage Registers
116(1)
33 Shift Registers
117(1)
33 Shift Right Shift Register
117(4)
33 Parallel In/Serial Out -- Serial In/Parallel Out Left Shift Registers
121(1)
33 Linear Feedback Shin Registers
122(2)
33 Designing Finite-State Machines -- Part 2: Counting and Dividing
124(7)
33 Dividers
124(1)
33 Divide by Two
124(1)
33 Asynchronous Dividers and Counters
125(2)
33 Synchronous Dividers and Counters
127(1)
33 Johnson Counters
128(1)
33 Two-Stage Johnson Counter
129(1)
33 Three-or Greater Stage Johnson Counter
130(1)
33 Practical Considerations -- Part 1: Timing in Latches and Flip-Flops
131(4)
33 Gated Latches
131(1)
33 Flip-Flops
132(1)
33 Propagation Delays
132(1)
33 Timing Margin
133(2)
33 Practical Considerations -- Part 2: Clocks and Clock Distribution
135(6)
33 The Source
135(1)
33 Frequency
135(2)
33 Precision and Stability
137(1)
33 Designing a Clock System
137(1)
33 Single-Phase Clocks
137(1)
33 Multiple-Phase Clocks
138(3)
33 More Than Four Phases
141(1)
33 Multiple Clocks Versus Multiple Phases
141(1)
33 Gating the Clock
141(1)
33 Testing Sequential Circuits
141(11)
33 The Finite-State Machine Model Revisited
142(1)
33 Sequential Circuit Test -- A First Look
142(3)
33 Defining Homing and Transfer Sequences
145(3)
33 Scan Design Techniques
148(1)
33 Boundary Scan-Extending Scan-Path Techniques
149(3)
33 Summary
152(1)
33 Review Questions
152(1)
33 Thought Questions
153(2)
33 Problems
155(10)
33 Memories and the Memory Subsystem
165(50)
33 Introduction
165(1)
33 Classifying Memory
166(1)
33 A General Memory Interface
167(1)
33 ROM Overview
168(1)
33 Read Operation
169(1)
33 Static RAM Overview
169(2)
33 Write Operation
171(1)
33 Read Operation
171(1)
33 Dynamic RAM Overview
171(2)
33 Read Operation
172(1)
33 Write Operation
172(1)
33 Refresh Operation
172(1)
33 Chip Organization
173(1)
33 Terminology
173(3)
33 A Memory Interface in Detail
176(1)
33 An SRAM Design
177(3)
33 The Memory Array
177(2)
33 Reading and Writing
179(1)
33 Write
179(1)
33 Read
179(1)
33 A DRAM Design
180(3)
33 DRAM Timing Analysis
181(1)
33 Core Components
181(1)
33 DRAM Refresh
182(1)
33 The DRAM Memory Interface
183(5)
33 Refresh Timing
183(1)
33 Refresh Address
184(1)
33 Refresh Arbitration
185(3)
33 The Memory Map
188(1)
33 Memory Subsystem Architecture
189(1)
33 Basic Concepts of Caching
190(2)
33 Locality of Reference
190(2)
33 Cache System Architecture
192(1)
33 Designing a Cache System
192(1)
33 A High-Level Description
192(1)
33 Caching -- A Direct Mapped Implementation
193(3)
33 Caching -- An Associative Mapping Cache Implementation
196(2)
33 Caching -- A Block-Set Associative Mapping Cache Implementation
198(1)
33 Dynamic Memory Allocation
199(3)
33 Swapping
200(1)
33 Overlays
200(1)
33 Multiprogramming
201(1)
33 Fixed
201(1)
33 Variable Number
202(1)
33 Testing Memories
202(6)
33 RAM Memory
204(2)
33 ROM Memory
206(2)
33 Summary
208(1)
33 Review Questions
208(1)
33 Thought Questions
209(1)
33 Problems
210(5)
33 An Introduction to Software Modeling
215(28)
33 Introduction
215(1)
33 An Introduction to UML
216(1)
33 UML Diagrams
217(1)
33 Use Cases
218(2)
33 Writing a Use Case
219(1)
33 Class Diagrams
220(3)
33 Class Relationships
221(1)
33 Inheritance or Generalization
221(1)
33 Interface
221(1)
33 Containment
222(1)
33 Dynamic Modeling with UML
223(1)
33 Interaction Diagrams
223(2)
33 Call and Return
224(1)
33 Create and Destroy
224(1)
33 Send
225(1)
33 Sequence Diagrams
225(1)
33 Fork and Join
226(1)
33 Branch and Merge
227(1)
33 Activity Diagram
228(1)
33 Slate Chart Diagrams
228(5)
33 Events
228(1)
33 State Machines and State Chart Diagrams
229(1)
33 UML State Chart Diagrams
230(1)
33 Transitions
230(1)
33 Guard Conditions
231(1)
33 Composite States
232(1)
33 Dynamic Modeling with Structured Design Methods
233(4)
33 Brief Introduction to the Structured Design Philosophy
233(1)
33 Data and Control Flow Diagrams
234(1)
33 The Elements
234(3)
33 Summary
237(1)
33 Review Questions
237(2)
33 Thought Questions
239(1)
33 Problems
240(3)
33 The Software Side -- Part 1: The C Program
243(36)
33 Introduction
243(1)
33 Software and Its Manifestations
243(6)
33 Combining Hardware and Software
244(1)
33 High-Level Language
245(1)
33 Preprocessor
245(1)
33 Cross Compiler
246(1)
33 Assembler
246(1)
33 Linker and Loader
247(1)
33 Storing
248(1)
33 An Embedded C Program
249(1)
33 A Program
249(1)
33 Developing Embedded Software
249(1)
33 Abstraction
250(1)
33 C Building Blocks
250(18)
33 Fundamental Data -- What's in a Name?
250(1)
33 Identifiers in C
250(1)
33 Defining Variables -- Giving Them a Name and a Value
251(1)
33 Defining Variables -- Giving Them a Type, Scope, and Storage Class
252(1)
33 Type
252(6)
33 The const Qualifier
258(1)
33 Variable Names Revisited
259(1)
33 Type Conversions
259(2)
33 Scope
261(2)
33 Storage Class
263(5)
33 C Program Structure
268(5)
33 Separate Compilation
268(1)
33 Translation Units
268(1)
33 Linking and Linkage
269(1)
33 Linking
269(1)
33 Linkage
270(1)
33 Where C Finds Functions
271(1)
33 Makefiles
271(1)
33 Standard and Custom Libraries
272(1)
33 Debug and Release Builds
272(1)
33 Summary
273(1)
33 Review Questions
273(1)
33 Thought Questions
274(1)
33 Problems
275(4)
33 The Software Side -- Part 2: Pointers and Functions
279(52)
33 Introduction
279(1)
33 Bitwise Operators
280(5)
33 Bit Manipulation Operations
280(1)
33 Testing, Resetting, and Setting Bits
281(3)
33 Arithmetic Operations
284(1)
33 Pointer Variables and Memory Addresses
285(11)
33 Getting Started
285(5)
33 Simple Pointer Arithmetic
290(3)
33 Pointer Comparison
293(1)
33 Const Pointers
293(1)
33 Generic and NULL Pointers
294(1)
33 Generic Pointers
294(1)
33 Null Pointers
295(1)
33 The Function
296(10)
33 Function Header
296(1)
33 Function Name
296(1)
33 Arguments or Parameter List
296(1)
33 Return
296(1)
33 The Function Body
297(1)
33 Using a Function
297(4)
33 Pass By Value
301(2)
33 Pass By Reference
303(1)
33 Function Name Scope
304(1)
33 Function Prototypes
304(2)
33 Nesting Functions
306(1)
33 Pointers to Functions
306(4)
33 Structures
310(10)
33 The Struct
311(2)
33 Initialization
313(1)
33 Access
313(1)
33 Operations
314(1)
33 Structs as Data Members
314(1)
33 Accessing Members
314(1)
33 Initialization and Assignment
315(1)
33 Functions
315(3)
33 Pointers to Structs
318(1)
33 Accessing Members
318(1)
33 Passing Structs and Pointers to Structs
319(1)
33 The Interrupt
320(4)
33 The Interrupt Control Flow
320(1)
33 The Interrupt Event
320(1)
33 The Interrupt Service Routine -- ISR
321(1)
33 The Interrupt Vector Table
321(2)
33 Control of the Interrupt
323(1)
33 Enable-Disable
323(1)
33 Recognizing an Interrupting Event
323(1)
33 Interrupting and Masking an Interrupting Event
324(1)
33 Summary
324(1)
33 Review Questions
324(2)
33 Thought Questions
326(1)
33 Problems
327(4)
33 Developing the Foundation
33 Safety, Security, Reliability, and Robust Design
331(72)
33 Introduction
331(2)
33 Safety
333(1)
33 Reliability
334(2)
33 Faults, Errors, and Failures
336(1)
33 Another Look at Reliability
337(1)
33 Some Real-World Examples
337(3)
33 Big Word Small Register
338(1)
33 It's My Turn -- Not Yours
338(1)
33 Where Do I Put My Stuff?
339(1)
33 Single-Point and Common Mode Failure Model
340(1)
33 Safe Specifications
340(1)
33 Safe, Secure, and Robust Designs
341(6)
33 Understanding System Requirements
341(1)
33 Managing Essential Information
342(1)
33 The Review Process
343(1)
33 Bug Lists
344(1)
33 Errors and Exceptions
344(3)
33 Use the Available Tools
347(1)
33 Safe and Robust Designs -- The System
347(1)
33 System Functional Level Considerations
347(3)
33 Control and Alarm Subsystems
347(1)
33 Memory and Bus Subsystems
348(1)
33 Data Faults and the Communications Subsystem
349(1)
33 Power and Reset Subsystems
349(1)
33 Peripheral Device Subsystems
349(1)
33 Clock Subsystem
349(1)
33 System Architecture Level Considerations
350(3)
33 Fail Operational2/Fail Operational Capability
350(1)
33 Same Design
351(1)
33 Alternative Designs
351(1)
33 Reduced Capability
352(1)
33 Lightweight Redundancy
352(1)
33 Monitor Only
352(1)
33 Busses -- The Subsystem Interconnect
353(2)
33 The Star Configuration
353(1)
33 The Multidrop Bus Configuration
353(1)
33 The Ring Configuration
354(1)
33 Data and Control Faults -- Data Boundary Values
355(1)
33 Type Conformance
355(1)
33 Boundary Values
355(1)
33 Data and Control Faults -- The Communications Subsystem
356(11)
33 Damaged Data
356(1)
33 Detectability
356(1)
33 Extent
357(1)
33 Response
358(1)
33 Managing Damaged Data
358(1)
33 Parity
358(1)
33 Linear Codes
358(9)
33 The Power Subsystem
367(3)
33 Full Operation
368(1)
33 Reduced Operation
368(1)
33 Backup Operation
369(1)
33 Peripheral Devices -- Built-in Self-Test (BIST)
370(4)
33 Self-Tests
370(1)
33 Busses
371(2)
33 ROM Memory
373(1)
33 RAM Memory
373(1)
33 Peripheral Devices
373(1)
33 What to Do If a Test Fails?
373(1)
33 Failure Modes and Effects Analysis
374(2)
33 Security -- Look Behind You
376(1)
33 Understanding the Problem -- Looking at the System
376(1)
33 Analyzing the Problem -- Looking at Potential Vulnerabilities
377(1)
33 Understanding the Problem -- Looking at the Attacks
378(4)
33 Looking at the Software
378(3)
33 Looking at the Hardware
381(1)
33 Dealing with the Problem -- Protecting Against the Attacks
382(14)
33 Protecting the Software
382(1)
33 First Steps
382(2)
33 Second Steps
384(1)
33 Third Steps
385(1)
33 Fourth Steps
386(1)
33 Software Testing Tools
387(1)
33 Protecting the Hardware
388(1)
33 First Steps
388(1)
33 Second Steps
388(2)
33 Third Steps
390(1)
33 Protecting a Network Interface
390(1)
33 First Steps
391(1)
33 Second Steps
391(4)
33 Firewall
395(1)
33 Closure
396(1)
33 Tomorrow
396(1)
33 Summary
397(1)
33 Review Questions
397(1)
33 Thought Questions
398(1)
33 Problems
399(4)
33 Embedded Systems Design and Development -- Hardware-Software Co-Design
403(104)
33 Introduction
404(1)
33 System Design and Development
405(3)
33 Getting Ready -- Start Thinking
406(1)
33 Getting Started
407(1)
33 Life-Cycle Models
408(5)
33 The Waterfall Model
409(1)
33 The V Cycle Model
410(1)
33 The Spiral Model
411(1)
33 Rapid Prototyping -- Incremental
412(1)
33 Problem Solving -- Six Steps To Design
413(1)
33 Hardware--Software Co-Design
414(3)
33 The First Steps
415(1)
33 Traditional Embedded Systems Development
415(2)
33 History
417(1)
33 Advantages of the Co-Design Methodology
417(1)
33 Co-Design Process Overview
418(1)
33 The Co-Design Process
419(3)
33 Laying the Foundation
422(1)
33 Identifying the Requirements
423(2)
33 Formulating the Requirements Specification
425(12)
33 The Environment
426(1)
33 Characterizing External Entities
427(1)
33 The System
427(2)
33 Characterizing the System
429(8)
33 The System Design Specification
437(11)
33 The System
439(1)
33 Quantifying the System
439(9)
33 System Requirements Versus System Design Specifications
448(1)
33 Executing the Hardware-Software Co-Design Process
449(1)
33 Functional Decomposition
449(3)
Identifying the Functions
452(1)
Functional Decomposition
452(2)
33 Partitioning and Mapping to an Architecture
454(11)
33 Initial Thoughts
455(2)
33 Coupling
457(1)
33 Cohesion
458(1)
33 A Few More Considerations
459(1)
33 Approaches to Partitioning and Mapping
459(1)
33 The Approach
460(1)
33 The Method
460(5)
33 Evaluation of a Partition
465(1)
33 Architectural Design
465(4)
33 Mapping Functions to Hardware
465(1)
33 Hardware and Software Specification and Design
466(3)
33 Functional Model Versus Architectural Model
469(1)
33 The Functional Model
469(1)
33 The Architectural Model
470(1)
33 The Need for Both Models
470(1)
33 Modeling Tools and Languages for Co-Design
470(10)
33 Why are We Modeling?
471(1)
33 What are We Modeling?
471(1)
33 Characterizing the Model
472(1)
33 Classes of MoCs
472(1)
33 Conceptual Model
472(1)
33 Analytic Model
472(1)
33 A Look at Some Models
473(1)
33 The Logic Circuit
474(1)
33 The Random Access Machine-RAM
474(1)
33 The Turing Machine
474(1)
33 The Pushdown Automaton Machine
475(1)
33 The Basic Finite State Machine
475(1)
33 Communicating Finite State Machines
476(1)
33 Extended FSM
476(1)
33 Co-Design FSM
477(1)
33 Program State Machines
478(1)
33 UML State Charts
479(1)
33 Petri Nets
479(1)
33 Kahn Process Network
480(1)
33 Control Flow -- Data Flow -- CDFG Graphs
480(1)
33 Co-Synthesis
480(6)
33 Constraints
481(1)
33 Software Synthesis
482(1)
33 System Characterization
483(1)
33 Scheduling
483(1)
33 Synthesis Methods
483(3)
33 Implementing The System
486(2)
33 Analyzing the System Design
486(1)
33 Static Analysis
486(1)
33 Dynamic Analysis
487(1)
33 Co-Simulation
488(7)
33 Tools Supporting Modeling
489(1)
33 Types of Simulations
489(1)
33 Approaches
490(1)
33 Detailed Processor Model
490(1)
33 Cycle-Based Simulation -- Bus Model
491(1)
33 Instruction Set Architecture -- ISA Mode
491(1)
33 Compiled Model
491(1)
33 Hardware Model
492(1)
33 Master Slave Model
492(1)
33 Distributed Co-Simulation
493(1)
33 Heterogeneous Modeling -- The Ptolemy Project
493(1)
33 Domains
494(1)
33 Classes of MoCs
494(1)
33 Co-Verification
495(2)
33 Hardware--Software Co-Verification
495(1)
33 Tools Supporting Simulation and Verification
496(1)
33 Basic Capabilities
496(1)
33 Levels of Abstraction
496(1)
33 Other Considerations
497(2)
33 Capitalization and Reuse
497(1)
33 Capitalization
497(1)
33 Reuse
497(1)
33 Requirements Traceability and Management
498(1)
33 Requirements Traceability
498(1)
33 Requirements Management
498(1)
33 Archiving the Project
499(1)
33 Summary
500(1)
33 Review Questions
500(2)
33 Thought Questions
502(1)
33 Problems
503(4)
33 Hardware Test and Debug
507(34)
33 Introduction
507(1)
33 Some Vocabulary
507(1)
33 Putting Together a Strategy
508(1)
33 Formulating a Plan
509(2)
33 Formalizing the Plan -- Writing a Specification
511(1)
33 Executing the Plan -- The Test Procedure and Test Cases
512(1)
33 Applying the Strategy -- Egoless Design
513(1)
33 Applying the Strategy -- Design Reviews
513(1)
33 Applying the Strategy -- Module Debug and Test
514(2)
33 Black Box Tests
514(1)
33 White Box Tests
515(1)
33 Gray Box Tests
515(1)
33 Applying the Strategy -- The First Steps
516(3)
33 The Parts
516(1)
33 Initial Tests and Measurements -- Before Applying Power
517(1)
33 Initial Tests and Measurements -- Immediately After Applying Power
518(1)
33 Applying the Strategy -- Debugging and Testing
519(2)
33 The Reset System
519(1)
33 The Clocks and Timing
519(1)
33 The Inputs and Outputs
519(1)
33 Sudden Failure during Debugging
520(1)
33 Testing and Debugging Combinational Logic
521(1)
33 Path Sensitizing
521(4)
33 Single Variable--Single Path
522(1)
33 Testing
522(1)
33 Debugging
523(1)
33 Single Variable--Two Paths
523(2)
33 Masking and Untestable Faults
525(1)
33 Single Variable--Multiple Paths
526(1)
33 Bridge Faults
527(2)
33 Debugging -- Sequential Logic
529(2)
33 Scan Design Testing
531(2)
33 Boundary-Scan Testing
533(2)
33 Memories and Memory Systems
535(1)
33 Applying the Strategy -- Subsystem and System Test
535(1)
33 Applying the Strategy -- Testing for Our Customer
536(1)
33 Alpha and Beta Tests
536(1)
33 Verification Tests
536(1)
33 Validation Tests
536(1)
33 Acceptance Tests
537(1)
33 Production Tests
537(1)
33 Self-Test
537(1)
33 On Demand
537(1)
33 In Background
537(1)
33 Summary
538(1)
33 Review Questions
538(1)
33 Thought Questions
539(1)
33 Problems
540(1)
33 Doing the Work
33 Real-Time Kernels and Operating Systems
541(32)
33 Introduction
541(1)
33 Tasks and Tilings
542(2)
33 Programs and Processes
544(1)
33 The CPU Is a Resource
544(3)
33 Setting a Schedule
545(1)
33 Changing Context
546(1)
33 Threads -- Lightweight and Heavyweight
547(2)
33 A Single Thread
547(1)
33 Multiple Threads
548(1)
33 Sharing Resources
549(2)
33 Memory Resource Management
549(1)
33 System-Level Management
549(1)
33 Process-Level Management
550(1)
33 Reentrant Code
551(1)
33 Foreground / Background Systems
551(1)
33 The Operating System
551(2)
33 The Real-Time Operating System (RTOS)
553(1)
33 Operating System Architecture
553(2)
33 Tasks and Task Control Blocks
555(9)
33 The Task
555(1)
33 The Task Control Block
555(2)
33 A Simple Kernel
557(3)
33 Interrupts Revisited
560(4)
33 Memory Management Revisited
564(6)
33 Duplicate Hardware Context
565(2)
33 Task Control Blocks
567(1)
33 Stacks
567(1)
33 Runtime Stack
568(1)
33 Application Stacks
569(1)
33 Multiprocessing Slacks
569(1)
33 Summary
570(1)
33 Review Questions
570(1)
33 Thought Questions
571(1)
33 Problems
571(2)
33 Tasks and Task Management
573(52)
33 Introduction
573(1)
33 Time, Time-Based Systems, and Reactive Systems
574(3)
33 Time
574(1)
33 Reactive and Time-Based Systems
574(3)
33 Task Scheduling
577(3)
33 CPU Utilization
577(1)
33 Scheduling Decisions
578(1)
33 Scheduling Criteria
578(1)
33 Priority
578(1)
33 Turnaround Time
579(1)
33 Throughput
579(1)
33 Waiting Time
580(1)
33 Response Time
580(1)
33 Scheduling Algorithms
580(6)
33 Asynchronous Interrupt Event Driven
580(1)
33 Polled and Polled with a Timing Element
581(1)
33 State Based
581(1)
33 Synchronous Interrupt Event Driven
582(1)
33 Combined Interrupt Event Driven
582(1)
33 Foreground--Background
582(1)
33 Time-Shared Systems
583(1)
33 First-Come First-Served
583(1)
33 Shortest Job First
583(1)
33 Round Robin
583(1)
33 Priority Schedule
583(1)
33 Rate-Monotonic
583(1)
33 Earliest Deadline
584(1)
33 Least Laxity
585(1)
33 Maximum Urgency
585(1)
33 Real-Time Scheduling Considerations
586(1)
33 Algorithm Evaluation
586(3)
33 Deterministic Modeling
586(2)
33 Queuing Models
588(1)
33 Simulation
589(1)
33 Implementation
589(1)
33 Tasks, Threads, and Communication
589(10)
33 Getting Started
589(1)
33 Intertask / Interthread Communication
589(1)
33 Shared Variables
590(1)
33 Global Variables
590(1)
33 Shared Buffer
591(1)
33 Shared Double Buffer -- Ping-Pong Buffer
591(2)
33 Ring Buffer
593(1)
33 Mailbox
593(1)
33 Messages
594(1)
33 Communication
595(4)
33 Buffering
599(1)
33 Task Cooperation, Synchronization, and Sharing
599(11)
33 Critical Sections and Synchronization
600(4)
33 Flags
604(2)
33 Token Passing
606(1)
33 Interrupts
606(1)
33 Semaphores
607(2)
33 Process Synchronization
609(1)
33 Spin Lock and Busy Waiting
609(1)
33 Counting Semaphores
609(1)
33 Talking and Sharing in Space
610(4)
33 The Bounded Buffer Problem
610(2)
33 The Readers and Writers Problem
612(2)
33 Monitors
614(4)
33 Condition Variables
615(1)
33 Bounded Buffer Problem with Monitor
616(2)
33 Starvation
618(1)
33 Deadlocks
618(1)
33 Summary
618(1)
33 Review Questions
618(1)
33 Thought Questions
619(1)
33 Problems
620(5)
33 Deadlocks
625(20)
33 Introduction
625(1)
33 Sharing Resources
625(1)
33 System Model
626(1)
33 Deadlock Model
627(1)
33 Necessary Conditions
628(1)
33 A Graph Theoretic Tool -- The Resource Allocation Graph
628(3)
33 Handling Deadlocks
631(1)
33 Deadlock Prevention
631(2)
33 Mutual Exclusion
631(1)
33 Hold and Wait
632(1)
33 No Preemption
632(1)
33 Circular Wait
632(1)
33 Deadlock Avoidance
633(5)
33 Algorithms Based on the Resource Allocation Graph
634(1)
33 Banker's Algorithm and Safe States
635(3)
33 Deadlock Detection
638(2)
33 Detection in a Single-Instance Environment
638(1)
33 Deadlock Recovery
638(1)
33 Task Termination
639(1)
33 Resource Preemption
639(1)
33 Summary
640(1)
33 Review Questions
640(1)
33 Thought Questions
641(1)
33 Problems
641(4)
33 Performance Analysis and Optimization
645(70)
33 Introduction
645(1)
33 Getting Started
646(1)
33 Performance or Efficiency Measures
646(3)
33 Introduction
646(2)
33 The System
648(1)
33 Some Limitations
648(1)
33 Complexity Analysis -- A High-Level Measure
649(2)
33 The Methodology
651(1)
33 A Simple Experiment
651(1)
33 Working with Big Numbers
652(1)
33 Asymptotic Complexity
652(1)
33 Comparing Algorithms
652(3)
33 Big-O Notation
653(1)
33 Big-O Arithmetic
654(1)
33 Analyzing Code
655(4)
33 Constant Time Statements
655(1)
33 Looping Constructs
656(1)
33 For Loops
656(1)
33 While Loops
657(1)
33 Sequences of Statements
657(1)
33 Conditional Statements
658(1)
33 Function Calls
658(1)
33 Analyzing Algorithms
659(2)
33 Analyzing Search
659(1)
33 Linear Search
659(1)
33 Binary Search
660(1)
33 Analyzing Sort
660(1)
33 Selection Sort
660(1)
33 Quick Sort
661(1)
33 Analyzing Data Structures
661(1)
33 Array
661(1)
33 Linked List
662(1)
33 Instructions in Detail
662(9)
33 Getting Started
663(1)
33 Flow of Control
663(1)
33 Sequential
664(1)
33 Branch
664(1)
33 Loop
665(1)
33 Function Call
665(1)
33 Analyzing the Flow of Control-Two Views
666(1)
33 Sequential Flow
666(1)
33 Branch
666(1)
33 Loop
667(1)
33 Function Call
668(2)
33 Co-routine
670(1)
33 Interrupt Call
671(1)
33 Time, etc. -- A More Detailed Look
671(1)
33 Metrics
672(1)
33 Response Time
672(7)
33 Polled Loops
673(1)
33 Co-routine
674(1)
33 Interrupt-Driven Environment
674(1)
33 Preemptive Schedule
674(1)
33 Nonpreemptive Schedule
675(1)
33 Meeting Real-Time Constraints
675(1)
33 Deadline Monotonic Analysis
676(1)
33 Vocabulary
676(1)
33 Analysis
677(1)
33 Priority Ceiling Protocol
678(1)
33 Time Loading
679(3)
33 Instruction Counting
680(1)
33 Simulation
680(1)
33 Models
680(1)
33 Timers
681(1)
33 Instrumentation
681(1)
33 Memory Loading
682(2)
33 Memory Map
682(1)
33 Designing a Memory Map
683(1)
33 Instruction/Firmware Area
683(1)
33 RAM Area
683(1)
33 Stack Area
684(1)
33 Evaluating Performance
684(1)
33 Early Stages
685(1)
33 Mid-stages
685(1)
33 Later Stages
685(1)
33 Thoughts on Performance Optimization
685(1)
33 Questions to Ask
685(1)
33 Performance Optimization
686(1)
33 Common Mistakes
686(1)
33 Tricks of the Trade
687(5)
33 Hardware Accelerators
692(1)
33 Introduction -- Target Low Power
693(1)
33 Low Power -- A High-Level View
693(9)
33 Zero Power Consumption
694(1)
33 Static Power Consumption
694(1)
33 Sources of Static Power Consumption
694(1)
33 Addressing Static Power Consumption
695(1)
33 Dynamic Power Consumption
696(1)
33 Sources of Dynamic Power Consumption -- Hardware
697(4)
33 Sources of Dynamic Power Consumption -- Software
701(1)
33 Addressing Dynamic Power Consumption -- Hardware
702(4)
33 Power Management Schemes -- Hardware
703(1)
33 Advanced Configuration and Power Interface (ACPI)
704(1)
33 Dynamic Voltage and Frequency Scaling
705(1)
33 Addressing Dynamic Power Consumption -- Software
706(3)
33 Measuring Power Consumption
707(1)
33 Caches and Performance
708(1)
33 Trade-Offs
709(1)
33 Summary
709(1)
33 Review Questions
710(1)
33 Thought Questions
710(1)
33 Problems
711(4)
33 Developing the Foundation
33 Working Outside of the Processor I: A Model of Interprocess Communication
715(18)
33 Communication and Synchronization with the Outside World
715(1)
33 First Steps: Understanding the Problem
716(1)
33 Interprocess Interaction Revisited
717(2)
33 The Model
719(3)
33 Information
719(1)
33 Places
720(1)
33 Control and Synchronization
720(1)
33 Transport
721(1)
33 Exploring the Model
722(8)
33 The Transport Mechanism
722(1)
33 The Interconnection Topology
722(1)
33 Star
723(1)
33 Ring
724(3)
33 Control and Synchronization
727(1)
33 Information Flow
727(1)
33 Direction of Flow
727(1)
33 Magnitude of the Flow
728(1)
33 I/O Timing
729(1)
33 Software Device Drivers
729(1)
33 Places
729(1)
33 Summary
730(1)
33 Review Questions
730(1)
33 Thought Questions
730(3)
33 Working Outside of the Processor I: Refining the Model of Interprocess Communication
733(56)
33 Communication and Synchronization with the Outside World
733(1)
33 The Local Device Model
734(3)
33 Control, Synchronization, and Places
735(1)
33 A Serial Model
735(1)
33 A Parallel Model
736(1)
33 Information -- Data
737(1)
33 Transport
737(1)
33 Implementing the Local Device Model -- A First Step
737(8)
33 An Overview
737(1)
33 Main Memory Address Space
738(1)
33 I/O Ports
738(1)
33 Peripheral Processor
739(1)
33 Main Memory Address Space -- Memory-Mapped I/O
739(1)
33 Address Bus
740(1)
33 Data Bus
740(1)
33 Control Bus
740(1)
33 Read
741(1)
33 Write
741(1)
33 Bidirectional Bus
742(2)
33 I/O Polls -- Program-Controlled I/O
744(1)
33 The Peripheral Processor
744(1)
33 Implementing the Local Device Model -- A Second Step
745(2)
33 Information Interchange -- An Event
745(1)
33 Information Interchange -- A Shared Variable
746(1)
33 Information Interchange -- A Message
746(1)
33 Implementing an Event-Driven Exchange -- Interrupts and Polling
747(8)
33 Polling
747(2)
33 Interrupts
749(1)
33 Single Interrupt Line with Single Device
749(1)
33 Single Interrupt Line with Multiple Devices
749(4)
33 Multiple Interrupt Lines
753(1)
33 Masking Interrupts
754(1)
33 A Message
755(7)
33 Asynchronous Information Exchange
756(1)
33 Strobes
756(1)
33 Strobe with Acknowledge
757(1)
33 Full Handshake
757(1)
33 Resynchronization
758(1)
33 Analysis
759(1)
33 Synchronous Information Exchange
759(1)
33 Bit Synchronization
759(3)
33 The Remote Device Model
762(2)
33 Places and Information
764(1)
33 Control and Synchronization
764(1)
33 Transport
764(1)
33 Implementing the Remote Device Model -- A First Step
764(7)
33 The OSI and TCP/IP Protocol Stacks
765(2)
33 OSI -- Physical Layer
767(1)
33 OSI -- Data Link Layer
767(1)
33 TCP/IP -- Host to Network
767(1)
33 OSI -- Network Layer
767(1)
33 TCP/IP -- Internet Layer
767(1)
33 OSI -- Transport Layer
767(1)
33 TCP/IP -- Transport Layer
768(1)
33 OSI -- Session Layer
768(1)
33 OSI -- Presentation Layer
768(1)
33 OSI -- Application Layer
768(1)
33 TCP/IP-Application Layer
768(1)
33 The Models
769(1)
33 The Client-Server Model
769(1)
33 The Peer-to-Peer Model
769(1)
33 The Group Multicast Model
770(1)
33 Implementing the Remote Device Model -- A Second Step
771(2)
33 The Messages
771(1)
33 The Message Structure
771(1)
33 Message Control and Synchronization
772(1)
33 The Header
772(1)
33 The Transfer Scheme
772(1)
33 Working with Remote Tasks
773(8)
33 Preliminary Thoughts on Working with Remote Tasks
773(1)
33 Local vs. Remote Addresses and Data
774(1)
33 Repeated Task Execution
774(1)
33 Node Failure, Link Failure, Message Loss
775(1)
33 Procedures and Remote Procedures
775(1)
33 Calling a Remote Procedure -- RFC Semantics
775(2)
33 The Transport
777(1)
33 Message Source and Destination
777(1)
33 The Protocol
778(1)
33 RPC Interlace Definition
779(1)
33 Node Failure, Link Failure, Message Loss
779(1)
33 Node Failure and Loss
779(1)
33 Message Loss
780(1)
33 Group Multicast Revisited
781(1)
33 Atomic Multicast
781(1)
33 Reliable Multicast
781(1)
33 Connecting to Distributed Processes -- Pipes, Sockets, and Streams
782(2)
33 Pipes
782(1)
33 Sockets
782(2)
33 Stream Communication
784(1)
33 Summary
784(1)
33 Review Questions
784(1)
33 Thought Questions
785(1)
33 Problems
786(3)
33 Working Outside of the Processor II: Interfacing to Local Devices
789(48)
33 Shared Variable I/O -- Interfacing to Peripheral Devices
789(1)
33 The Shared Variable Exchange
790(1)
33 Generating Analog Signals
790(6)
33 Binary Weighted Digital-to-Analog Converter
791(3)
33 R/2R Ladder Digital-to-Analog Converter
794(2)
33 Common Measurements
796(1)
33 Voltage
796(1)
33 Current
796(1)
33 Resistance
797(1)
33 Measuring Voltage
797(9)
33 Dual Slope Analog-to-Digital Conversion
797(4)
33 Successive Approximation Analog-to-Digital Conversion
801(2)
33 Sample and Hold
803(1)
33 VCO Analog-to-Digital Conversion
804(2)
33 Measuring Resistance
806(2)
33 Measuring Current
808(1)
33 Measuring Temperature
808(4)
33 Sensors
809(1)
33 Making the Measurement
809(1)
33 Working with Nonlinear Devices
810(2)
33 Generating Digital Signals
812(3)
33 Motors and Motor Control
812(1)
33 DC Motors
812(2)
33 Servo Motors
814(1)
33 Stepper Motors
814(1)
33 Controlling DC and Servo Motors
815(6)
33 DC Motors
815(1)
33 Servo Motors
816(1)
33 Controlling Stepper Motors
817(2)
33 Motor Drive Circuitry
819(2)
33 Motor Drive Noise
821(1)
33 LEDs and LED Displays
821(3)
33 Individual LEDs
821(1)
33 Multi-LED Displays
822(2)
33 Measuring Digital Signals
824(7)
33 The Approach
824(1)
33 Working with Asynchronous Signals
825(1)
33 Buffering Input Signals
826(1)
33 Inside vs. Outside
827(1)
33 Measuring Frequency and Time Interval
827(1)
33 Measuring the Period-An Internal Implementation
827(1)
33 Measuring the Period -- An External Implementation
828(1)
33 Counting for a Known Interval -- An Internal Implementation
829(1)
33 Counting for a Known Interval -- An External Implementation
830(1)
33 Summary
831(1)
33 Review Questions
831(1)
33 Thought Questions
832(1)
33 Problems
832(5)
33 Working Outside of the Processor III: Interfacing to Remote Devices
837(32)
33 Common Network-Based I/O Architectures
837(1)
33 Network-Based Systems
838(1)
33 RS-232/EIA-232 -- Asynchronous Serial Communication
838(7)
33 Introduction
838(1)
33 The EIA-232 Standard
839(1)
33 What It Is ...
840(1)
33 What they Think It Is ...
840(2)
33 EIA-232 Addressing
842(1)
33 Asynchronous Serial Communication
842(1)
33 Configuring the Interface
842(1)
33 Data Recovery and Timing
843(1)
33 EIA-232 Interface Signals
844(1)
33 An Implementation
845(1)
33 The Universal Serial Bus -- Synchronous Serial Communication
845(10)
33 Background
846(1)
33 The Universal Serial Bus Architecture
846(1)
33 The Universal Serial Bus Protocol
847(1)
33 USB Devices
848(1)
33 Transfer Types
848(1)
33 Device Descriptors
849(1)
33 Network Configuration
850(1)
33 USB Transactions
851(1)
33 USB Interface Signals
852(1)
33 The Physical Environment
853(1)
33 Low-Speed Cables
853(1)
33 High-Speed Cables
853(1)
33 Cables and Cable Power
853(1)
33 Detecting Device Attachment and Speed
854(1)
33 Differential Pair Signaling
855(1)
33 Implementation
855(1)
33 I2C -- A Local Area Network
855(5)
33 The Architecture
855(1)
33 Electrical Considerations
856(1)
33 Basic Operation
857(1)
33 Flow of Control
858(1)
33 Multiple Masters
859(1)
33 Arbitration
859(1)
33 Synchronization
859(1)
33 Using the I2C Bus
859(1)
33 The Controller Area Network -- The CAN Bus
860(5)
33 The Architecture
860(1)
33 Electrical Considerations
861(1)
33 Message Types
862(1)
33 Message Format
862(1)
33 Basic Operation
863(1)
33 Synchronization
863(1)
33 Error Management
863(1)
33 Transmission and Arbitration
863(1)
33 Using the CAN Bus
864(1)
33 Summary
865(1)
33 Review Questions
865(1)
33 Thought Questions
866(1)
33 Problems
866(3)
33 Programmable Logic Devices
869(24)
33 Introduction
869(1)
33 Why Use Programmable Logic Devices?
870(1)
33 Basic Concepts
871(3)
33 Basic Configurations
874(2)
33 The (P)ROM
874(1)
33 Programmable Array Logic -- PAL
875(1)
33 Programmable Logic Array -- PLA
875(1)
33 Programmable Logic Sequencer -- PLS
876(1)
33 PLA vs. PAL vs. (P)ROM
876(1)
33 Programmable and Reprogrammable Technologies
876(3)
33 Programmable Technologies
876(1)
33 Reprogrammable Technologies
877(2)
33 Architectures
879(6)
33 PLDs
879(2)
33 CPLD
881(1)
33 FPGAs
882(3)
33 The Design Process
885(1)
33 Design Examples
885(6)
33 Lane Departure Detection Implementation and Acceleration
886(1)
33 Introduction
886(1)
33 Requirements
886(1)
33 Design
887(1)
33 Results
888(1)
33 Section Summary
888(1)
33 Local Area Tracking System -- LATS with uCLinux™ OS
888(1)
33 Introduction
888(1)
33 Requirements
889(1)
33 System Description
889(1)
33 Design Procedure
890(1)
33 Test Plan
890(1)
33 Summary
891(1)
33 Review Questions
891(1)
33 Thought Questions
892(1)
33 Practical Considerations Signal Behavior in the Real World -- Part 1 -- Noise and Crosstalk
893(16)
33 Introduction -- The Real World Again
893(1)
33 Noise
893(1)
33 Power Supply and Ground Noise
894(9)
33 Common Path Noise
894(1)
33 Power Distribution Wiring
895(1)
33 Resistance
895(1)
33 Inductance
896(1)
33 Board Level Bypass
897(2)
33 Computing the Board Level Bypass Capacitor
899(1)
33 Local Bypass Capacitors
900(1)
33 Computing the Local Bypass Capacitors
901(2)
33 Power and Ground Planes
903(1)
33 Crosstalk and Loops
903(4)
33 Crosstalk
904(1)
33 Preventing or Reducing Crosstalk
905(1)
33 Loops
905(2)
33 Summary
907(1)
33 Review Questions
907(1)
33 Problems
908(1)
33 Practical Considerations Signal Behavior in the Real World -- Part 2 -- High-Speed Signaling
909(72)
33 Introduction -- The Real World Yet Again
909(1)
33 The Problem
910(4)
33 Terminology
911(1)
33 Noise
911(1)
33 Switching Noise
911(1)
33 Crosstalk
912(1)
33 Ringing
912(1)
33 Attenuation or Loss
912(1)
33 Jitter
912(1)
33 Period Jitter
912(1)
33 Cycle-to-Cycle Jitter
912(1)
33 Nth-cycle Jitter
912(1)
33 Aperture Time
912(1)
33 Reflection
912(1)
33 Ground Bounce
913(1)
33 Transmitter Output Timing Jitter
913(1)
33 Capacitive Loading
913(1)
33 The Working Environment
914(10)
33 The Signaling Environment
914(3)
33 The PCB Environment
917(1)
33 Microstrip
918(1)
33 Stripline
918(1)
33 Signal Propagation
919(1)
33 Distributed Versus Lumped
920(1)
33 Point-to-Point Wiring
921(1)
33 Signal Distortion
921(2)
33 Electromagnetic Interference in Point-to-Point Wiring
923(1)
33 EMI to Crosstalk in Point-to-Point Wiring
923(1)
33 The Transmission Line
924(13)
33 The Lossless Transmission Line
926(1)
33 The Finite Transmission Line
927(2)
33 Transient Input
929(1)
33 Reflections -- Termination Schemes
930(1)
33 Unterminated Signal Path
931(1)
33 Low Source Impedance -- TTL/ECL Drivers
931(1)
33 High Source Impedance -- CMOS Drivers
932(1)
33 Parallel Termination -- End Terminated
932(2)
33 End Terminated -- Biased Termination
934(1)
33 End Terminated -- Split Termination
934(2)
33 Source Terminated -- Series Termination
936(1)
33 Differential Signaling
937(1)
33 Environment
937(1)
33 Signals in the Nonideal (Real) World
937(2)
33 Other Considerations
939(1)
33 Examining the Environment
940(3)
33 Test Equipment
940(1)
33 The Eye Diagram
940(1)
33 Generating the Eye Diagram
940(2)
33 Interpreting the Eye Diagram
942(1)
33 Back of the Envelope Examination
943(2)
33 A First Step Check List
943(1)
33 Routing and Topology
943(1)
33 Topology Alternatives
944(1)
33 Summary
945(1)
33 Review Questions
946(1)
33 Thought Questions
946(1)
33 Problems
947(2)
33 Verilog Overview: The Verilog Hardware Description Language
949(32)
33 Introduction
949(2)
33 Creating a Verilog Program
951(1)
33 Some Concepts in a Verilog Source File
951(1)
33 Modules
951(1)
33 Module Name
952(1)
33 Inputs and Outputs Declarations
952(1)
33 Nets and Variables
953(1)
33 Declaring Multibit Signals
953(1)
33 Subsets of Multibit Expressions
954(1)
33 $display and $monitor Statements
955(1)
33 $stop and $finish Statements
955(1)
33 $time Statement
956(1)
33 Three Models -- The Gate Level, the Dataflow, and the Behavioral
956(1)
33 The Structural/Gate-Level Model
956(1)
33 Creating Modules
957(1)
33 Using Modules
958(1)
33 Delays
959(1)
33 Defining Constants
960(3)
33 The Dataflow Model
963(1)
33 Continuous Assignment
963(1)
33 Delays
964(2)
33 Operators
966(1)
33 The Behavioral Model
966(1)
33 Program Structure
966(2)
33 Procedural Assignment
968(1)
33 Delays
969(4)
33 Flow of Control
973(3)
33 Testing and Verifying the Circuit
976(1)
33 The Circuit Module
977(1)
33 The Test Module
977(2)
33 Clocks and Resets
979(1)
33 The Test Bench
979(1)
33 Performing the Simulation
979(1)
33 Summary
980(1)
Further Reading 981(10)
Index 991
JAMES K. PECKOL, PHD is a Principal Lecturer in the Department of Electrical Engineering at the University of Washington – Seattle, USA, where he has been named Teacher of the Year three times and Outstanding Faculty twice. He is also the founder of Oxford Consulting, Ltd., a product design and development consulting firm, is a member of Who's Who in the World, and has been presented with the Marquis Who's Who Lifetime Achievement Award.