Shows readers how to gain the competitive edge in the integrated circuit marketplace
This book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard-cell libraries and shows design engineers and managers how to use this knowledge to beat the competition.
Engineering the CMOS Library reveals step by step how the generic, foundry-provided standard-cell library is built, and how to extract value from existing std-cells and EDA tools in order to produce tighter-margined, smaller, faster, less power-hungry, and more yield-producing integrated circuits. It explores all aspects of the digital design kit, including the different views of CMOS std-cell libraries along with coverage of IO libraries, memory compilers, and small analog blocks. Readers will learn:
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How to work with overdesigned std-cell libraries to improve profitability while maintaining safety
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How functions usually found in std-cell libraries cover the design environment, and how to add any missing functions
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How to harness the characterization technique used by vendors to add characterization without having to get it from the vendor
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How to use verification and validation techniques to ensure proper descriptive views and even fix inconsistencies in vendor release views
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How to correct for possible conflicts arising from multiple versions and different vendor sources in any given integrated circuit design
Complete with real-world case studies, examples, and suggestions for further research, Engineering the CMOS Library will help readers become more astute designers.
PREFACE xi ACKNOWLEDGMENTS xiii 1 INTRODUCTION 1 1.1 Adding
Project-Specific Functions, Drive Strengths, Views, and Corners 4 1.2 What Is
a DDK? 5 2 STDCELL LIBRARIES 9 2.1 Lesson from the Real World: Manager's
Perspective and Engineer's Perspective 9 2.2 What Is a Stdcell? 11 2.3
Extended Library Offerings 32 2.4 Boutique Library Offerings 36 2.5 Concepts
for Further Study 37 3 IO LIBRARIES 39 3.1 Lesson from the Real World: The
Manager's Perspective and the Engineer's Perspective 39 3.2 Extension Capable
Architectures versus Function Complete Architectures 40 3.3 Electrostatic
Discharge Considerations 43 3.4 Concepts for Further Study 50 4 MEMORY
COMPILERS 52 4.1 Lesson from the Real World: The Manager's Perspective and
the Engineer's Perspective 52 4.2 Single Ports, Dual Ports, and ROM: The
Compiler 55 4.3 Nonvolatile Memories: The Block 58 4.4 Special-Purpose
Memories: The Custom 60 4.5 Concepts for Further Study 62 5 OTHER FUNCTIONS
63 5.1 Lesson from the Real World: The Manager's Perspective and the
Engineer's Perspective 63 5.2 Phase-Locked Loops, Power-On Resets, and Other
Small-Scale Integration Analogs 66 5.3 Low-Power Support Structures 69 5.4
Stitching Structures 71 5.5 Hard, Firm, and Soft Boxes 75 5.6 Concepts for
Further Study 78 6 PHYSICAL VIEWS 80 6.1 Lesson from the Real World: The
Manager's Perspective and the Engineer's Perspective 80 6.2 Picking an
Architecture 82 6.3 Measuring Density 86 6.4 The Need and the Way to Work
with Fabrication Houses 89 6.5 Concepts for Further Study 92 7 SPICE 95 7.1
Lesson from the Real World: The Manager's Perspective and the Engineer's
Perspective 95 7.2 Why a Tool More Than 40 Years Old Is Still Useful 99 7.3
Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye 102
7.4 Sufficient Parasitics 106 7.5 Concepts for Further Study 107 8 TIMING
VIEWS 109 8.1 Lesson from the Real World: The Manager's Perspective and the
Engineer's Perspective 109 8.2 Performance Limits and Measurement 110 8.3
Default Versus Conditional Arcs 110 8.4 Break-Point Optimization 112 8.5 A
Word on Setup and Hold 115 8.6 Failure Mechanisms and Roll-Off 122 8.7
Supporting Efficient Synthesis 124 8.8 Supporting Efficient Timing Closure
131 8.9 Design Corner Specific Timing Views 134 8.10 Nonlinear Timing Views
are so "Old Hat" ... 140 8.11 Concepts for Further Study 142 9 POWER VIEWS
145 9.1 Lesson from the Real World: The Manager's Perspective and the
Engineer's Perspective 145 9.2 Timing Arcs Versus Power Arcs 147 9.3 Static
Power 148 9.4 Real Versus Measured Dynamic Power 150 9.5 Should Power Be
Built as a Monotonic Array? 153 9.6 Best-Case and Worst-case Power Views
Versus Best-Case and Worst-Case Timing Views 155 9.7 Efficiently Measuring
Power 156 9.8 Concepts for Further Study 158 10 NOISE VIEWS 160 10.1 Lesson
from the Real World: The Manager's Perspective and the Engineer's Perspective
160 10.2 Noise Arcs Versus Timing and Power Arcs 162 10.3 The Easy Part 165
10.4 The Not-So-Easy Part 166 10.5 Concepts for Further Study 168 11 LOGICAL
VIEWS 170 11.1 Lesson from the Real World: The Manager's Perspective and the
Engineer's Perspective 170 11.2 Consistency Across Simulators 171 11.2.1
Efficient Testing 175 11.3 Consistency with Timing, Power & Noise Views 177
11.4 Concepts for Further Study 180 12 TEST VIEWS 181 12.1 Lesson from the
Real World: The Manager's Perspective and the Engineer's Perspective 181 12.2
Supporting Reachability 184 12.3 Supporting Observability 189 12.4 Concepts
for Further Study 191 13 CONSISTENCY 193 13.1 Lesson from the Real World:
The Manager's Perspective and the Engineer's Perspective 193 13.2 Validating
Views across a Library 195 13.3 Validating Stdcells Across a Technology Node
199 13.4 Validating Libraries Across Multiple Technology Nodes 204 13.5
Concepts for Further Study 208 14 DESIGN FOR MANUFACTURABILITY 209 14.1
Lesson from the Real World: The Manager's Perspective and the Engineer's
Perspective 209 14.2 What is DFM? 211 14.3 Concepts for Further Study 224 15
VALIDATION 226 15.1 Lesson from the Real World: The Manager's Perspective
and the Engineer's Perspective 226 15.2 Quality Levels 229 15.3 Concepts for
Further Study 236 16 PLAYING WITH THE PHYSICAL DESIGN KIT: USUALLY "AT YOUR
OWN RISK" 237 16.1 Lesson from the Real World: The Manager's Perspective and
the Engineer's Perspective 237 16.2 Manipulating Models 240 16.3 Added
Unsupported Devices 243 16.4 Concepts for Further Study 245 17 TAGGING AND
REVISIONING 247 17.1 Lesson from the Real World: The Manager's Perspective
and the Engineer's Perspective 247 17.2 Tagging and Time Stamps 248 17.3
Metadata, Directory Structures, and Pointers 254 17.4 Concepts for Further
Study 258 18 RELEASING AND SUPPORTING 260 18.1 Lesson from the Real World:
The Manager's Perspective and the Engineer's Perspective 260 18.2 When Is
Test Silicon Needed for Verification? 263 18.3 Sending the Baby Out the Door
265 18.4 Multiple Quality Levels on the Same Design 269 18.5 Supporting "Bug
Fixes" 271 18.6 Concepts for Further Study 274 19 OTHER TOPICS 276 19.1
Lesson from the Real World: The Manager's Perspective and the Engineer's
Perspective 276 19.2 Supporting High-Speed Design 279 19.3 Supporting
Low-Power Design 283 19.4 Supporting Third-Party Libraries 286 19.5
Supporting Black Box Third-Party IP (Intellectual Property) Design 289 19.6
Supporting Multiple Library Design 292 19.7 Concepts for Further Study 293
20 COMMUNICATIONS 295 20.1 Manager's Perspective 295 20.2 Customer's
Perspective 298 20.3 Vendor's Perspective 300 20.4 Engineer's Perspective 301
20.5 Concepts for Further Study 302 20.6 Conclusions 302 APPENDIX I MINIMUM
LIBRARY SYNTHESIS VERSUS FULL-LIBRARY SYNTHESIS OF A FOUR-BIT FLASH ADDER 305
APPENDIX II PERTINENT CMOS BSIM SPICE PARAMETERS WITH UNITS AND DEFAULT
LEVELS 311 APPENDIX III DEFINITION OF TERMS 313 APPENDIX IV ONE POSSIBLE
MEANS OF FORMALIZED MONTHLY REPORTING 317 INDEX 319
David Doman is Circuit Manager at GlobalFoundries in Austin, Texas. He has more than thirty years of experience in semiconductor intellectual property design and development.
