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Engineer's Guide to Automated Testing of High-Speed Interfaces, Second Edition Unabridged edition [Kõva köide]

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  • Formaat: Hardback, 706 pages
  • Ilmumisaeg: 30-Apr-2016
  • Kirjastus: Artech House Publishers
  • ISBN-10: 1608079856
  • ISBN-13: 9781608079858
Teised raamatud teemal:
Engineer's Guide to Automated Testing of High-Speed Interfaces, Second Edition Unabridged editionSuurem pilt
  • Formaat: Hardback, 706 pages
  • Ilmumisaeg: 30-Apr-2016
  • Kirjastus: Artech House Publishers
  • ISBN-10: 1608079856
  • ISBN-13: 9781608079858
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781608079858.html
Märksõnad:
Providing a complete introduction to the state of the art in high-speed digital testing with automated test equipment (ATE), this practical resource is the first book to focus exclusively on this increasingly important topic. Featuring clear examples, this one-stop reference covers all critical aspects of the subject, from high-speed digital basics to test fixture design. This in-depth volume also discusses more advanced ATE topics, such as focus calibration and testing of high-speed bidirectional interfaces with a dual transmission line approach. This highly valuable book is packed with over 500 illustrations, more than 130 equations, and detailed appendices covering key concepts

Introducing engineers to the characterization and production testing of high-speed input/output digital interfaces using automated test equipment, Moreira and Werkmann do not just list the test requirements for these interfaces and propose test implementations, but also offer some background on why the test requirements are defined the way they are. Their topics include high-speed digital basics, automated testing equipment instrumentation for digital applications, tests and measures, test fixture design, and advanced topics. Annotation ©2016 Ringgold, Inc., Portland, OR (protoview.com)
Preface to the Second Edition xix
Preface to the First Edition xxi
1 Introduction 1(12)
1.1 Characterization and Design Verification
3(2)
1.2 Production Testing
5(1)
1.3 Accuracy and Correlation
5(1)
1.4 The ATE Test Fixture
6(1)
1.5 The Future
7(2)
1.5.1 TSV Technology
8(1)
1.5.2 Silicon Photonics
9(1)
1.5.3 Millimeter-Wave Wireless Communications
9(1)
References
9(4)
2 High-Speed Digital Basics 13(50)
2.1 High-Speed Digital Signaling
13(7)
2.1.1 Out-of-Band Signaling
14(1)
2.1.2 Data Eye Diagram
15(3)
2.1.3 Differential Signaling
18(1)
2.1.4 Transmission Line Termination
18(2)
2.2 Time and Frequency-Domains
20(5)
2.2.1 The Concept of Bandwidth and Its Pitfalls
23(2)
2.3 Bit Error Rate
25(3)
2.4 Jitter
28(16)
2.4.1 Jitter Histogram
29(2)
2.4.2 Jitter Categorization
31(8)
2.4.3 Amplitude Noise and Conversion to Timing Jitter
39(2)
2.4.4 Jitter in the Frequency-Domain
41(3)
2.5 Classification of High-Speed I/O Interfaces
44(4)
2.5.1 Common Clock Interfaces
45(1)
2.5.2 At-Cycle Source Synchronous Interfaces
46(1)
2.5.3 Forwarded Clock Interfaces
46(1)
2.5.4 Embedded Clock Interfaces
47(1)
2.6 Hardware Building Blocks and Concepts
48(10)
2.6.1 Phase Locked Loop (PLL)
48(3)
2.6.2 Delay Locked Loop (DLL)
51(1)
2.6.3 Clock and Data Recovery (CDR)
51(3)
2.6.4 Pre-Emphasis/De-Emphasis and Equalization
54(4)
2.7 Multilevel Signaling
58(2)
References
60(3)
3 High-Speed Interface Standards 63(68)
3.1 PCI Express
64(22)
3.1.1 Application Areas
64(1)
3.1.2 PCI Express Fundamentals
64(4)
3.1.3 PCI Express Details
68(3)
3.1.4 PCI Express Protocol
71(4)
3.1.5 Electrical Specifications
75(4)
3.1.6 ATE Test Requirements
79(2)
3.1.7 Test Support
81(2)
3.1.8 Test Challenges
83(3)
3.2 XDR DRAM
86(14)
3.2.1 Application Areas
86(1)
3.2.2 XDR Fundamentals
86(1)
3.2.3 XDR DRAM Details
87(4)
3.2.4 XDR Protocol
91(7)
3.2.5 Electrical Specifications
98(1)
3.2.6 ATE Test Requirements
98(1)
3.2.7 Test Support
99(1)
3.2.8 Test Challenges
99(1)
3.3 GDDR SDRAM
100(20)
3.3.1 Application Areas
100(1)
3.3.2 GDDR Fundamentals
100(1)
3.3.3 GDDR5 Details
101(6)
3.3.4 GDDR5 Protocol
107(7)
3.3.5 Electrical Specifications
114(2)
3.3.6 ATE Test Requirements
116(1)
3.3.7 Test Support
116(1)
3.3.8 Test Challenges
117(3)
3.4 MIPI Standards
120(6)
3.4.1 MIPI C-PHY v1.0
120(6)
3.5 Other High-Speed Digital Interface Standards
126(2)
References
128(3)
4 ATE Instrumentation for Digital Applications 131(38)
4.1 ATE Timing Architectures
136(4)
4.1.1 High-Frequency Clock Timing Architecture
136(1)
4.1.2 Variable Frequency Clock Timing Architecture
137(1)
4.1.3 Phase Accumulator Timing Architecture
138(2)
4.2 Digital Pin Electronics ATE Card
140(14)
4.2.1 CDR and Phase Tracking
143(1)
4.2.2 Equalization
144(1)
4.2.3 Time Measurement Unit
144(1)
4.2.4 Timing Jitter Injection
145(2)
4.2.5 Amplitude Noise and Common-Mode Voltage Injection
147(1)
4.2.6 Bidirectional and Simultaneous Bidirectional Support
148(2)
4.2.7 Protocol Engine
150(1)
4.2.8 ATE Loopback Path
150(1)
4.2.9 Parametric Measurements
150(4)
4.3 Sampler/Digitizer ATE Card
154(3)
4.3.1 Aliasing
154(1)
4.3.2 Digitizer
155(1)
4.3.3 Sampler
156(1)
4.4 Parametric Measurements with Sampled Data
157(7)
4.4.1 Undersampling of High-Speed I/O Signals
157(2)
4.4.2 Coherency Equation
159(1)
4.4.3 Capturing Digital Waveforms
160(3)
4.4.4 Special Considerations for Coherent Sampling with Digital ATE Channels
163(1)
4.5 Power Supplies
164(3)
References
167(2)
5 Tests and Measurements 169(88)
5.1 Bit and Pattern Alignment
169(7)
5.1.1 Bit Alignment
171(3)
5.1.2 Pattern Alignment
174(2)
5.2 Functional Test
176(2)
5.3 Shmoo Tests
178(3)
5.4 Fundamental Driver Tests
181(19)
5.4.1 Rise/Fall Time
181(1)
5.4.2 Data Eye Diagram
182(9)
5.4.3 BER Bathtub Curve
191(3)
5.4.4 Skew
194(3)
5.4.5 Pre-Emphasis and De-Emphasis Measurement
197(3)
5.5 Driver Jitter Tests
200(23)
5.5.1 Jitter Histogram
200(1)
5.5.2 RMS Jitter
201(1)
5.5.3 Peak-to-Peak Jitter
202(1)
5.5.4 Drawbacks of the Error Count Approach for Jitter Measurements
203(3)
5.5.5 Measuring the Jitter Spectrum
206(2)
5.5.6 Random and Deterministic Jitter Separation
208(9)
5.5.7 Measuring the Data-Dependent Jitter
217(1)
5.5.8 Measuring Bounded Uncorrelated Jitter
218(1)
5.5.9 Jitter Measurement Correlation
218(3)
5.5.10 Driver Amplitude Noise
221(2)
5.6 Fundamental Receiver Tests
223(7)
5.6.1 Setup and Hold
224(3)
5.6.2 Receiver Sensitivity
227(3)
5.7 Receiver Jitter Tolerance
230(9)
5.7.1 Random Jitter Tolerance
231(1)
5.7.2 Sinusoidal Jitter Tolerance
232(2)
5.7.3 Data-Dependent Jitter (DDJ) Tolerance
234(2)
5.7.4 Bounded Uncorrelated Jitter (BUJ) Tolerance
236(1)
5.7.5 Testing the Receiver Equalizer
237(2)
5.8 PLL Characterization
239(5)
5.8.1 Jitter Transfer
239(2)
5.8.2 Frequency Offset
241(1)
5.8.3 Spread Spectrum Clocking
242(2)
5.9 Other Tests
244(6)
5.9.1 Impedance Tests
244(5)
5.9.2 Return Loss
249(1)
5.10 Power Consumption During IC Testing
250(1)
5.11 Measurement Errors
251(1)
References
252(5)
6 Production Testing 257(36)
6.1 Golden Device
258(1)
6.2 System-Level Test
259(1)
6.3 Instrument-Based Testing: At-Speed ATE
259(7)
6.3.1 Physical Implementation
260(2)
6.3.2 Parametric Testing
262(4)
6.4 Instrument-Based Testing: Low-Speed ATE
266(16)
6.4.1 Double Data Clocking
266(3)
6.4.2 Channel Multiplexing
269(1)
6.4.3 Near-End Loopback Testing
269(13)
6.5 Instrument-Based Testing: Bench Instrumentation
282(1)
6.6 Active Test Fixture
282(2)
6.7 Multi-site Testing
284(5)
6.7.1 Driver Sharing for Multi-site Applications
285(4)
References
289(4)
7 Support Instrumentation 293(62)
7.1 Oscilloscopes
293(5)
7.1.1 Real-Time Oscilloscopes
293(1)
7.1.2 Equivalent-Time Sampling Oscilloscopes
294(4)
7.2 Bit Error Rate Tester
298(1)
7.3 Time Interval Analyzer
299(1)
7.4 Time-Domain Reflectrometry/Transmission (TDR/TDT)
300(1)
7.5 Spectrum Analyzer
300(2)
7.6 Signal Source Analyzer
302(1)
7.7 Vector Network Analyzer
302(1)
7.8 Arbitrary Waveform and Function Generators
303(1)
7.9 Noise Generators
304(3)
7.10 Sinusoidal Clock Sources
307(1)
7.11 Clock and Data Recovery
308(1)
7.12 Protocol Analyzer
308(1)
7.13 Switch Matrix
309(1)
7.14 Isolation Transformer
309(3)
7.15 Connecting Bench Instrumentation to an ATE System
312(5)
7.15.1 Signal Integrity
312(2)
7.15.2 Synchronization
314(2)
7.15.3 External Reference Clock Impact on Jitter Measurements
316(1)
7.16 Coaxial Cables and Connectors
317(12)
7.16.1 Coaxial Cables
317(7)
7.16.2 Coaxial Connectors
324(5)
7.17 Accessories
329(23)
7.17.1 Power Splitters and Power Dividers/Combiners
330(3)
7.17.2 Attenuators, DC Blocking Capacitors, and Terminations
333(3)
7.17.3 Bias Network
336(2)
7.17.4 Pickoff Tee
338(1)
7.17.5 ESD/Overload Protection
338(2)
7.17.6 Delay Lines
340(2)
7.17.7 Filters
342(2)
7.17.8 Probes
344(4)
7.17.9 Balun
348(1)
7.17.10 Frequency Doublers
349(3)
7.17.11 Frequency Dividers
352(1)
References
352(3)
8 Test Fixture Design 355(106)
8.1 Test Fixtures
357(5)
8.1.1 Test Fixture to ATE Interconnect
361(1)
8.2 High-Speed Design Effects
362(16)
8.2.1 Reflections Due to Impedance Mismatches
362(2)
8.2.2 Conductor Losses
364(4)
8.2.3 Dielectric Losses
368(8)
8.2.4 Crosstalk
376(2)
8.3 Impedance Controlled Routing
378(5)
8.3.1 Microstrip and Striplines
378(4)
8.3.2 Differential Routing
382(1)
8.4 Stack-Up
383(3)
8.5 Via Transitions
386(10)
8.5.1 Interlayer Vias
392(2)
8.5.2 Pogo Pin Vias
394(2)
8.6 Coaxial Connector Footprint Design
396(1)
8.7 DUT BGA Ballout
397(4)
8.8 Relays
401(4)
8.9 Bidirectional Layout
405(3)
8.10 Sockets
408(12)
8.10.1 Sockets for Package-on-Package (POP) Applications
414(1)
8.10.2 Socket Electrical Characterization
415(2)
8.10.3 Socket Cleaning
417(1)
8.10.4 Space Transformers for ATE Test Fixtures
417(1)
8.10.5 Socket Temperature Control
417(3)
8.11 Power Distribution Network Design
420(25)
8.11.1 Power Planes
426(5)
8.11.2 Decoupling Capacitors
431(9)
8.11.3 Inductors and Ferrite Beads
440(1)
8.11.4 Socket Inductance
440(1)
8.11.5 Power Distribution Network Design
441(1)
8.11.6 Power Distribution Network Simulation
442(1)
8.11.7 Disconnecting Bulk Capacitance for Faster DC Measurements
443(1)
8.11.8 Stability of the ATE DUT Power Supply
444(1)
8.12 HIFIX
445(1)
8.13 Wafer Probing
446(6)
References
452(9)
9 Advanced ATE Topics 461(70)
9.1 ATE Specifications and Calibration
461(10)
9.1.1 Accuracy and Resolution
461(1)
9.1.2 Understanding OTA and EPA
462(1)
9.1.3 Linearity and Edge Placement Accuracy
463(2)
9.1.4 Calibration
465(6)
9.2 Multiplexing of ATE Channels
471(2)
9.3 Focus Calibration
473(11)
9.3.1 Skew Calibration
474(4)
9.3.2 Data Eye Height Calibration
478(2)
9.3.3 Jitter Injection
480(2)
9.3.4 Data Eye Profile
482(2)
9.4 Testing of High-Speed Bidirectional Interfaces with a Dual Transmission Line Approach
484(5)
9.5 Including the DUT Receiver Data Recovery in Driver Tests
489(2)
9.6 DUT Reference Clock Jitter Attenuation Approaches
491(2)
9.7 Protocol-Awareness and Protocol-Based Testing
493(5)
9.8 Testing Multilevel Interfaces with Standard Digital ATE Pin Electronics
498(4)
9.9 Signal Path Characterization and Compensation
502(17)
9.9.1 Signal Path Loss Compensation: De-Embedding
502(5)
9.9.2 Characterization in the Frequency-Domain
507(1)
9.9.3 Signal Path Loss Compensation: Equalization
507(12)
9.10 Test Fixture and ATE Pin Electronics Co-Simulation
519(3)
9.11 ATE DC Level Adjustments
522(5)
9.11.1 Correction of Force Levels for DUT Input Pins
523(1)
9.11.2 Correction of Levels for DUT Output Pins
524(3)
References
527(4)
A Introduction to the Gaussian Distribution and Analytical Computation of the BER 531(12)
A.1 The Gaussian Distribution
532(3)
A.2 Computation of the BER for a System with Only Gaussian Random Jitter
535(3)
A.3 Computation of the a(BER) Value
538(2)
A.4 Properties of the Error Function erf(x) and Complementary Error Function erfc(x)
540(1)
References
541(2)
B The Dual Dirac Model and RJ/DJ Separation 543(10)
B.1 The Dual Dirac Jitter Model
543(4)
B.2 RJ/DJ Separation with the Q-Factor Algorithm
547(3)
References
550(3)
C Pseudo-Random Bit Sequences and Other Data Patterns 553(6)
C.1 Pseudo-Random Bit Sequences
553(3)
C.1.1 Challenges of the PRBS31 Data Pattern
556(1)
C.2 Pseudo-Random Word Sequences
556(1)
C.3 Other Important Patterns
556(1)
References
557(2)
D Coding, Scrambling, Disparity, and CRC 559(18)
D.1 Disparity
560(2)
D.2 8B/10B Coding
562(3)
D.3 128B/130B Coding
565(4)
D.3.1 128B/130B Ordered Set
566(1)
D.3.2 128B/130B Data Block
567(1)
D.3.3 128B/130B Scrambling
568(1)
D.4 Scrambling
569(2)
D.5 Error Detection
571(4)
D.5.1 Parity Bits
571(1)
D.5.2 Checksums
572(3)
References
575(2)
E Time-Domain Reflectometry and Time-Domain Transmission (TDR/TDT) 577(14)
E.1 TDR
578(4)
E.1.1 Measuring the Impedance of a Trace with a TDR
579(2)
E.1.2 Measuring the Round-Trip Delay of a Signal Trace
581(1)
E.1.3 Measuring Discontinuities on a Signal Path with a TDR
581(1)
E.1.4 Measuring the Return Loss with a TDR
582(1)
E.2 TDT
582(4)
E.2.1 Measuring the Step Response
583(1)
E.2.2 Measuring the Insertion Loss with a TDT
584(1)
E.2.3 Measuring Crosstalk Using a TDT and an Extra Sampler
585(1)
E.3 Differential TDR/TDT Measurements
586(2)
References
588(3)
F S-Parameters 591(14)
F.1 Simulating and Synthesizing Time-Domain Responses from S-Parameters
597(2)
F.2 S-Parameters of Coupled Differential Pairs and Structures
599(2)
F.3 S-Parameters: Calibration and De-Embedding
601(1)
References
602(3)
G Engineering CAD Tools 605(10)
G.1 Circuit Simulators
605(3)
G.2 3D EM Field Solvers
608(1)
G.3 2D Planar Field Solvers
608(2)
G.4 Power Integrity
610(1)
G.5 Model Generation
611(1)
G.6 Other Tools
612(2)
References
614(1)
H Test Fixture Evaluation and Characterization 615(30)
H.1 Measuring the Test Fixture Signal Performance
615(21)
H.1.1 Test Coupons
617(5)
H.1.2 Test Fixture Socket and Socket Via Field Probing Interposer
622(9)
H.1.3 Monitoring Interposer
631(5)
H.2 Measuring the Test Fixture Power Distribution Network
636(7)
H.2.1 Measuring the PDN Voltage
640(3)
References
643(2)
I Jitter Injection Calibration 645(16)
I.1 Sinusoidal Jitter Injection Calibration
645(8)
I.1.1 The J1/J0 Bessel Approach
646(4)
I.1.2 The RJ Subtraction Approach
650(3)
I.2 Random Jitter Injection Calibration
653(4)
I.3 ISI Jitter Injection Calibration
657(2)
References
659(2)
J Phase Noise, RMS Jitter, and Random Jitter 661(8)
References
667(2)
About the Authors 669(2)
Index 671
Jose Moreira is currently a senior engineer at Verigy R&D in Boeblingen. He has extensive experience in the ATE industry, where he has held several positions at Agilent Technologies and Verigy. Mr. Moreira received an M.S. in electrical and computer engineering from the Instituto Superior Tecnico of the Technical University of London.Hubert Werkmann is a principal consultant at Verigy Germany GmbH. Dr. Werkmann received a Diploma degree in computer science and a Ph.D. in engineering from the University of Stuttgart, Germany.