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Extending Moore's Law through Advanced Semiconductor Design and Processing Techniques [Kõva köide]

(University of Johannesburg, Gauteng, South Africa), , ,
  • Formaat: Hardback, 366 pages, kõrgus x laius: 234x156 mm, kaal: 540 g, 79 Tables, black and white; 20 Illustrations, color; 105 Illustrations, black and white
  • Ilmumisaeg: 27-Sep-2018
  • Kirjastus: CRC Press Inc
  • ISBN-10: 0815370741
  • ISBN-13: 9780815370741
Teised raamatud teemal:
Extending Moore's Law through Advanced Semiconductor Design and Processing TechniquesSuurem pilt
  • Formaat: Hardback, 366 pages, kõrgus x laius: 234x156 mm, kaal: 540 g, 79 Tables, black and white; 20 Illustrations, color; 105 Illustrations, black and white
  • Ilmumisaeg: 27-Sep-2018
  • Kirjastus: CRC Press Inc
  • ISBN-10: 0815370741
  • ISBN-13: 9780815370741
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780815370741.html
Märksõnad:
This book provides a methodological understanding of the theoretical and technical limitations to the longevity of Moores law. The book presents research on factors that have significant impact on the future of Moores law and those factors believed to sustain the trend of the last five decades. Research findings show that boundaries of Moores law primarily include physical restrictions of scaling electronic components to levels beyond that of ordinary manufacturing principles and approaching the bounds of physics. The research presented in this book provides essential background and knowledge to grasp the following principles:











Traditional and modern photolithography, the primary limiting factor of Moores law





Innovations in semiconductor manufacturing that makes current generation CMOS processing possible





Multi-disciplinary technologies that could drive Moore's law forward significantly





Design principles for microelectronic circuits and components that take advantage of technology miniaturization





The semiconductor industry economic market trends and technical driving factors

The complexity and cost associated with technology scaling have compelled researchers in the disciplines of engineering and physics to optimize previous generation nodes to improve system-on-chip performance. This is especially relevant to participate in the increased attractiveness of the Internet of Things (IoT). This book additionally provides scholarly and practical examples of principles in microelectronic circuit design and layout to mitigate technology limits of previous generation nodes. Readers are encouraged to intellectually apply the knowledge derived from this book to further research and innovation in prolonging Moores law and associated principles.
Authors xi
Chapter 1 The Driving Forces Behind Moore's Law and Its Impact on Technology
1(32)
Wynand Lambrechts
Saurabh Sinha
Jassem Abdallah
Introduction
1(11)
The Inevitable Demise of Dennard's Scaling Law
2(2)
Power Consumption in CMOS Inverters
4(5)
Returning to Moore's Law
9(3)
Technical and Economic Factors Driving Moore's Law
12(4)
Technical Factors Driving Moore's Law
12(2)
Economic Factors Driving Moore's Law
14(2)
The Limitations of Moore's Law
16(4)
Photolithography
17(2)
Interconnects and Heat Generation
19(1)
Engineering Challenges
19(1)
Next-Generation Technologies
20(6)
Optical Interconnects
20(3)
Three-Dimensional Design
23(3)
Future-Generation Technologies
26(1)
Molecular Electronics
26(1)
Graphene
26(1)
Spintronics
26(1)
Quantum Computing
27(1)
Conclusion
27(1)
References
28(5)
Chapter 2 The Economics of Semiconductor Scaling
33(34)
Wynand Lambrechts
Saurabh Sinha
Jaco Prinsloo
Jassem Abdallah
Introduction
33(29)
The Economics of Geometric Scaling of Substrates and Dies
34(12)
The Wafer Manufacturing Industry
46(1)
The Move to 17.7 Inch (450 mm/18 Inch) Wafers
47(4)
The Economics of Device Scaling/Feature Scaling
51(3)
General Manufacturing Operating Costs
54(2)
Running a Foundry Optimally
56(3)
Considering Die and Wafer Yield to Keep Driving Moore's Law
59(2)
Integrated Circuits: A Complex Business
61(1)
Conclusion
62(1)
References
63(4)
Chapter 3 The Importance of Photolithography for Moore's Law
67(34)
Wynand Lambrechts
Saurabh Sinha
Jassem Abdallah
Introduction
67(3)
Photolithography Light Sources
70(3)
Mercury Lamps
71(1)
Excimer Lasers
72(1)
Laser-Pulsed Plasma
73(1)
Simplified Process Flow for Patterning Semiconductor Levels
73(2)
Basic Principles of Lithographic Imaging Systems
75(11)
Optical Lithography Resolution
80(1)
Optical Lithography f-Number and Numerical Aperture
81(1)
Optical Lithography Depth of Focus
82(2)
Optical Lithography Photomask Protection (Pellicles)
84(2)
Lithography Techniques
86(5)
Contact Lithography
86(1)
Proximity Lithography
87(1)
Projection Lithography
88(1)
E-Beam Lithography
89(1)
G-Line lithography
90(1)
Mine Lithography
90(1)
DUV and EUV
90(1)
Light-Sensitive Photoresist
91(6)
Positive Photoresist Patterning
95(1)
Negative Photoresist Patterning
96(1)
Completing the Patterning Process
97(1)
Conclusion
97(1)
References
98(3)
Chapter 4 Photolithography Enhancements
101(40)
Wynand Lambrechts
Saurabh Sinha
Jassem Abdallah
Introduction
101(1)
Photolithography Resolution-Enhancement Techniques
102(14)
Immersion Photolithography (Single Exposure)
102(5)
Extreme UV Lithography
107(3)
Electron-Beam Lithography
110(6)
Advanced Photolithography Processing Techniques
116(12)
Pitch-Split Multiple Exposure Patterning
117(4)
Sidewall Image Transfer
121(2)
Directed Self-Assembly Patterning
123(5)
Optical Proximity Correction and Resolution Enhancement Techniques
128(3)
Material and Processing-Based Patterning Limitations
131(2)
Metrology-Based OPC Verification and Design Rule Checks
133(1)
Conclusion
134(1)
References
135(6)
Chapter 5 Future Semiconductor Devices: Exotic Materials, Alternative Architectures and Prospects
141(40)
Wynand Lambrechts
Saurabh Sinha
Jassem Abdallah
Jaco Prinsloo
Introduction
141(7)
Optoelectronic Waveguides and Photonic Crystals
143(2)
Molecular Electronics
145(2)
Spintronics
147(1)
Solid-State Quantum Computing
147(1)
Graphene-Based Electronic Circuits
148(2)
Optoelectronics: Waveguides and Photonic Crystals
150(5)
Molecular Electronics
155(2)
Spintronic Devices
157(3)
Solid-State Quantum Computing
160(16)
The Principles of Quantum Computing
160(3)
Quantum Gates
163(6)
Applications of Quantum Computing
169(1)
Shor's Algorithm
170(3)
Other Quantum Algorithms
173(1)
Quantum Codes and Quantum Cryptography
174(2)
Conclusion
176(1)
References
176(5)
Chapter 6 Microelectronic Circuit Thermal Constrictions Resulting from Moore's Law
181(34)
Wynand Lambrechts
Saurabh Sinha
Introduction
181(8)
CMOS Active and Passive Power Dissipation
189(2)
Aggressively Scaled CMOS Leakage Currents
191(1)
Subthreshold Leakage Current
192(3)
Reverse-Bias pn-Junction Leakage Current
195(2)
Gate Oxide Tunneling Leakage Currents
197(8)
The Schottky Barrier Height
200(2)
Direct Tunneling Current
202(3)
Tunneling Field-Effect Transistors
205(2)
Hot-Carrier Injection From the Substrate to the Gate Oxide
207(2)
Gate-Induced Drain Leakage
209(1)
Conclusion
210(2)
References
212(3)
Chapter 7 Microelectronic Circuit Enhancements and Design Methodologies to Facilitate Moore's Law -- Part 1
215(32)
Wynand Lambrechts
Saurabh Sinha
Introduction
215(6)
Microelectronic Circuit Component Footprints
221(1)
Transistor Optimizations
222(22)
The Impact of Transistor Scaling and Geometry on Noise
225(3)
Physical Layout Properties of the MOSFET
228(2)
Multiple-Finger Transistor Geometries
230(1)
Reduced Polysilicon Gate Resistance
231(1)
Reduced Drain and Source Area and Perimeter
232(2)
Improved MOS Transistor Frequency Response
234(1)
Improved Transistor Matching
234(1)
Transistor Layout Matching
235(1)
Common Centroid and Interdigitating Transistor Matching
236(5)
Shallow Trench Isolation Stress in Transistors
241(1)
Transistor Layout Checklist
241(3)
Conclusion
244(1)
References
245(2)
Chapter 8 Micro -- Part II
247(44)
Wynand Lambrechts
Saurabh Sinha
Introduction
247(3)
Integrated Resistor Optimizations
250(15)
Integrated Resistor Layout
250(1)
Resistance/Sheet Resistance of the Integrated Resistor
250(3)
Measurement of Layer Sheet Resistance and Contact Resistance
253(2)
Bridge Test Structure (Sheet Resistance)
255(1)
The Kelvin Structure (Contact Resistance)
256(1)
Integrated Resistor Parasitic Components
257(2)
Noise in Integrated Resistors
259(2)
Resistor Layout Optimizations and Matching
261(1)
Interdigitated Integrated Resistors
262(1)
Common-Centroid Integrated Resistors
263(1)
Dummy Elements
263(2)
MOS Capacitor Optimization
265(19)
Integrated Capacitor Layout
265(2)
MOS Capacitor Operating Regions
267(1)
Surface Accumulation
268(1)
Surface Depletion
269(1)
Weak Inversion (Threshold of Inversion Condition)
270(2)
Capacitor Layout Optimizations
272(12)
Inductor Optimizations
284(2)
Integrated Circuit Inductor Layout
284(2)
Conclusion
286(2)
References
288(3)
Chapter 9 The Evolving and Expanding Synergy Between Moore's Law and the Internet-of-Things
291(34)
Wynand Lambrechts
Saurabh Sinha
Introduction
291(7)
The Limitations of the IoT
298(2)
M2M Communication and the IoT
300(2)
Remote Device Management Challenges
302(4)
IoT Core Energy Efficiency
306(7)
Energy-Efficient IoT Receivers
313(9)
Tuned RF Receiver Architecture
313(2)
The Superheterodyne RF Receiver Architecture
315(3)
Super-Regenerative Receivers
318(4)
Conclusion
322(1)
References
323(2)
Chapter 10 Technology Innovations Driven by Moore's Law
325(20)
Wynand Lambrechts
Saurabh Sinha
Introduction
325(17)
Nvidia Volta 12 nm Graphics Processing Units
327(1)
3D NAND Storage
328(6)
Intel Corporation 10 nm Process Technology
334(3)
Samsung/Qualcomm 10 nm Transistors
337(1)
IBM Research 5 nm Transistors
338(2)
Wind River/Intel Corporation Industrial IoT Infrastructure
340(1)
Berkeley Lab 1 nm Carbon Nanotube
340(2)
Conclusion
342(2)
References
344(1)
Index 345
Johannes Wynand Lambrechts, SMIEEE, obtained his B.Eng., M.Eng., and Ph.D. degrees in Electronic Engineering from the University of Pretoria (UP), South Africa. He achieved his M.Eng. with distinction. He has authored 2 publications in peer-reviewed journals and has presented at various local and international conferences. Wynand is the lead author on two books in the fields on sustainable energy and in microelectronic engineering, published by an international publisher. He has co-authored two contributing chapters in another book in the field of green energy and technology. He previously held a position as an electronic engineer at Denel Dynamics, a state-owned company in South Africa. He is currently employed by SAAB Grintek Defence, and is also serving as a part-time research associate at the University of Johannesburg (UJ), South Africa.



Saurabh Sinha, PhD(Eng), Pr Eng, SMIEEE, FSAIEE, FSAAE, Prof Sinha obtained his B. Eng, M. Eng and Ph.D. degrees in Electronic Engineering from the University of Pretoria (UP). As a published researcher, he has authored or co-authored over 110 publications in peer-reviewed journals and at international conferences. Prof Sinha served UP for over a decade; his last service being as Director of the Carl and Emily Fuchs Institute for Microelectronics, Department of Electrical, Electronic and Computer Engineering. On 1 October 2013, Prof Sinha was appointed as Executive Dean of the Faculty of Engineering and the Built Environment (FEBE) at the University of Johannesburg (UJ). Prof Sinha is currently the UJ Deputy Vice-Chancellor: Research and Internationalisation. Among other leading roles, Prof Saurabh Sinha also served the IEEE as a Board of Director and IEEE Vice-President: Educational Activities.



Jassem Abdallah received his BSc in Chemical Engineering from The University of Texas at Austin with honors (undergraduate research thesis), and both his MSc and PhD in Chemical Engineering from the Georgia Institute of Technology. He completed postdoctoral research assignments at the Georgia Institute of Technology, the IBM Corporation, and the University of Johannesburg. His research background spans both Materials Science Engineering and Process Development Engineering, with a focus on semiconductor technology and organic electronic applications. He has several years of research experience working in both academic-scale, 100 mm class 100 cleanroom facilities as well as state-of-the-art 300 mm class 10 semiconductor R&D facilities. Jassem Abdallah's research focuses on the development of processes and functional materials for microelectronics applications. He has publications, patents, and invention disclosures in the fields of advanced semiconductor patterning via Directed Self Assembly (DSA); novel methods of processing thin films containing functional materials; and chemical surface modification of polymers, thin films, and substrates.



Jaco Prinsloo received his B.Eng in Electronic Engineering from the University of Pretoria in 2015. He is currently employed as an embedded engineer and software developer, where his work focuses on the development of cryptographic technology.