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Fault-Tolerance and Reliability Techniques for High-Density Random-Access Memories [Kõva köide]

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  • Formaat: Hardback, 448 pages, kõrgus x laius x paksus: 243x183x22 mm, kaal: 830 g
  • Ilmumisaeg: 24-Jun-2002
  • Kirjastus: Prentice Hall
  • ISBN-10: 0130084654
  • ISBN-13: 9780130084651
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Fault-Tolerance and Reliability Techniques for High-Density Random-Access MemoriesSuurem pilt
  • Formaat: Hardback, 448 pages, kõrgus x laius x paksus: 243x183x22 mm, kaal: 830 g
  • Ilmumisaeg: 24-Jun-2002
  • Kirjastus: Prentice Hall
  • ISBN-10: 0130084654
  • ISBN-13: 9780130084651
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780130084651.html
Märksõnad:
The latest research and techniques for every form of memory fault tolerance are surveyed here, integrating techniques for manufacturing, online, and field fault tolerance. Focus is on practical circuit and design solutions, with accessible explanations of device physics and circuit design theory. Some topics include embedded RAM for SoC design, mechanisms underlying soft and hard failures, the impact of scalability on reliability, and error-correcting codes and circuit techniques for field fault tolerance. The book is of interest to design engineers, test engineers, manufacturers, and researchers involved in the design and test of high-density next-generation RAMs. Chakraborty is a researcher in communications systems technology. Mazumder teaches in the Department of Electrical Engineering and Computer Science at the University of Michigan-Ann Arbor. Annotation c. Book News, Inc., Portland, OR (booknews.com)

Muu info

To improve RAM reliability without compromising performance, cost, or space requirements, engineers are turning to advanced fault-tolerant techniques. Fault Tolerance and Reliability Techniques for High-Density Random-Access Memories surveys the latest advances in manufacturing, online, and field-related fault tolerance. Coverage includes new research on soft and hard failures, modeling and analysis of manufacturing yield, built-in self-diagnosis and repair, flexible redundancy, ECC, mitigating radiation-induced single-event effects, structured custom design solutions, and more.
Preface xi
Acknowledgments xvii
Reliability and Fault Tolerance of Rams
1(38)
Introduction
2(1)
Impact of Scaling on Reliability
3(14)
Supply voltage and power constraints
4(1)
Threshold voltage control
5(1)
Gate oxide reliability
5(2)
Hot carrier degradation
7(1)
Latchup susceptibility
7(1)
Soft errors
8(6)
Electrostatic discharge and electrical overstress
14(2)
Metallization reliability
16(1)
Defects, Faults, Errors, and Reliability
17(1)
Reliability and Quality Testing and Measurement
18(6)
AQL measurement
18(1)
Burn-in testing
19(1)
IDDQ and IDD testing
20(1)
Parametric testing
21(1)
Dynamic testing
21(3)
Reliability Characterization
24(1)
Reliability Prediction Procedures
25(5)
Reliability Simulation Tools
30(2)
Mechanisms for Permanent Device Failure
32(4)
Chip- and assembly-related failures
33(2)
Design-related failures
35(1)
Environment-related failures
35(1)
Safeguarding Against Failures
36(2)
Concluding Remarks
38(1)
Diagnosis, Repair, and Reconfiguration
39(76)
Introduction
40(1)
Diagnosis Algorithms
40(18)
Stuck-at faults in read/write circuitry
41(2)
Dominant 0/1 BFs in read/write circuitry
43(1)
SAFs and dominant-0 and dominant-1 BFs in address decoders
43(2)
Sequential stuck-open addressing faults
45(1)
SAFs, BFs and CFs in the memory cell array
46(1)
Coupling faults in the cell array
46(4)
Bridging faults in an array of memory chips
50(5)
Fault location algorithms for DRAMs
55(3)
Repair Algorithms
58(19)
Tarr's greedy algorithm
58(2)
Day's fault-driven, comprehensive redundancy algorithm
60(2)
Kuo and Fuchs's branch-and-bound algorithms
62(6)
Wey and Lombardi's graph-theoretic algorithm
68(3)
Fast test and repair algorithms by Haddad et al
71(2)
Neural net approaches
73(4)
Reconfiguration Techniques
77(3)
Repair Using Flash Eeprom Switches
80(3)
Flexible Redundancy
83(5)
Built-in Self-Diagnosis and Self-Repair
88(2)
Built-in Redundancy Analysis
90(2)
Built-in Self-Repair Architectures
92(18)
Hierarchical built-in self-repair
92(6)
Built-in self-repair using neural nets
98(3)
Various recently proposed BISR schemes
101(3)
Built-in self-diagnosis architecture supporting both hard and soft repair
104(6)
Concluding Remarks
110(1)
Problems
111(4)
Single-Event Effects and Their Mitigation
115(102)
Introduction
116(1)
Particles Causing Single-Event Effects
116(6)
Terrestrial environment
116(4)
Space environment
120(2)
Some Definitions
122(3)
Basic Mechanisms for Nondestructive Single-Event Effects
125(9)
Charge deposition
125(2)
Charge collection
127(7)
Ram Device Operation
134(8)
Dynamic RAM operation
134(3)
Static RAM operation
137(2)
Single-bit upsets
139(2)
Multibit upsets
141(1)
Critical Charge and Soft Error Rate
142(13)
Critical charge
142(1)
Nature of radiation source, energy, flux, and dose rate
143(5)
Collection efficiency
148(1)
Cell geometry
148(1)
Passivation layer characteristics
148(1)
Memory duty cycle
149(1)
Refresh periods
150(1)
Residual soft error rate and its dependence on scaling
150(2)
Dynamic nature of soft error rate and its dependence on clock frequency
152(2)
Dependence on diffusion, collection, and geometry of incidence
154(1)
Techniques Used for Mitigation of Single-Event Upsets
155(31)
System-level and circuit techniques
156(1)
Technology or device-level hardening techniques
157(2)
Process and circuit techniques for hardening SRAMs
159(13)
Process and circuit techniques for hardening DRAMs
172(14)
Experiments
186(6)
Alpha-particle experiments
186(1)
Broad-beam heavy-ion tests with ion accelerators
187(1)
Pulsed laser experiments
188(2)
Focused ion-beam irradiation
190(2)
Modeling and Simulation of Charge Collection
192(15)
Interaction models
193(1)
Models based on device physics
194(2)
Two-and three-dimensional and mixed-level simulations
196(2)
Circuit simulation of charge collection
198(1)
Multiple-device and mixed-level simulations
199(1)
Large-scale SEU simulation systems
200(1)
Case studies with device and mixed-level simulation
201(6)
Basic Mechanisms for Destructive Single-Event Effects
207(7)
Single-event latchup
208(2)
Single-event gate rupture
210(3)
Single-event burnout
213(1)
Single-event hard error
213(1)
Concluding Remarks
214(1)
Problems
215(2)
Error-Correcting Codes
217(60)
Introduction
218(1)
Theory of Error-Correcting Codes
218(31)
Concepts of error detection and correction
221(1)
Single-bit error-detecting code
221(1)
Single-bit error-correcting code
222(4)
Single-bit error-correcting and double-bit error-detecting codes
226(6)
Single-byte error-detecting codes
232(1)
Double-bit error-correcting codes
233(5)
Single-byte correcting, double-byte detecting codes
238(6)
Double-bit error-correcting, triple-bit error-detecting codes
244(2)
Extended error correction
246(2)
Comparison of some coding techniques
248(1)
Fault-Tolerant Design Techniques for Rams
249(6)
Bit scattering
250(1)
Sparing
251(1)
Complement/recomplement
251(1)
Consecutive correction
251(1)
Prestorage protection
252(2)
Fault alignment exclusion
254(1)
Page deallocation
255(1)
ECC Implementations
255(9)
Embedded ECC
255(4)
Nonembedded ECC
259(5)
Memory Reliability Evaluation Through Error Correction
264(2)
Memory organization
264(1)
Survival probability and estimated number of replacements needed
264(2)
Simulation of Memory Reliability and Fault Tolerance
266(6)
Memory model used by the simulator FTMS
267(2)
Error model used by the simulator FTMS
269(2)
Maintenance strategy
271(1)
FTMS program
271(1)
General-purpose memory reliability simulation
271(1)
Concluding Remarks
272(1)
Problems
273(4)
Yield Modeling and Prediction Techniques
277(44)
Introduction
278(1)
Yield Models
279(3)
Yield Loss Mechanisms
282(1)
Importance of Clustering Models
283(6)
Critical Area Simulation and Yield Calculation
289(14)
Analytical and statistical approaches
290(11)
Monte Carlo method
301(1)
Importance of yield simulation
302(1)
Effect of Redundancy and Error Correction on Yield
303(4)
Effect of Defect Density on Yield
307(1)
Effect of Defect Characteristics on Yield
308(1)
Effect of Device Scaling on Yield
309(2)
Relationship Between Yield and Reliability
311(2)
Yield Management Techniques
313(4)
Hardware used for automated defect detection
313(2)
Software techniques for yield improvement
315(2)
Concluding Remarks
317(1)
Problems
317(4)
Physical Design of Built-in Self-Repairable Rams
321(56)
Introduction
322(1)
Embedded Rams
323(2)
Built-in Self-Repairable Embedded Ram Physical Design
325(2)
Fault Modeling Based on Inductive Fault Analysis
327(2)
Circuit Implementation
329(5)
Column-multiplexed addressing
329(1)
Fast-access memory design
330(1)
Built-in self-test circuitry for IFA-9 test
331(1)
Built-in self-repair circuitry
332(2)
Self-test and self-repair control logic
334(1)
Characterization of a Custom Design Tool
334(32)
Delay
335(10)
Automatic transistor sizing and interconnect length minimization
345(1)
Testability analysis with the BIST approach
346(5)
Yield improvement
351(2)
Reliability improvement
353(3)
Area overhead
356(1)
Commercial embedded RAM data
356(10)
Multiobjective Optimization Approach for Ram Design
366(3)
Problem formulation
367(1)
Optimization algorithm
368(1)
Floorplanning of Parametrized Rectangular Macrocells
369(4)
Placement
371(1)
Routing
372(1)
Bist/Bisr for Other Types of Memories
373(1)
Concluding Remarks
373(2)
Problems
375(2)
Bibliography 377(42)
Index 419


KANAD CHAKRABORTY is currently Member of Technical Staff, Agere Systems Research (Communications Systems Technology Lab). He was formerly a software engineer and researcher with IBM's Electronic Design Automation Lab. His contributions include development of novel fault-tolerant memory architectures, algorithms for multiport memory testing, new design automation approaches, and neural network applications.

PINAKI MAZUMDER is Professor in the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor. His research interests include nanoelectronic and quantum electronic circuits and simulation, digital and analog testing, VLSI system design, and VLSI Layout Automation. He is a Fellow of IEEE. Mazumder and Chakraborty are co-authors of Testing and Testable Design of High-Density Random-Access Memories.