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Chapter 1 Concepts in Digital Systems |
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1 | (28) |
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1.1 What Is a Digital System? |
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1 | (1) |
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1.2 Views of a Digital System |
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2 | (2) |
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2 | (1) |
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1.2.2 The Personal Computer |
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3 | (1) |
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1.3 Introduction to Binary Numbers |
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4 | (2) |
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6 | (2) |
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1.5 Binary and Decimal Numbers |
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8 | (7) |
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1.5.1 Binary-to-Decimal Conversion |
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8 | (2) |
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1.5.2 Decimal-to-Binary Conversion |
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10 | (2) |
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12 | (2) |
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1.5.4 Hexadecimal Numbers |
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14 | (1) |
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15 | (4) |
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19 | (3) |
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22 | (1) |
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1.9 Hierarchical Plan for the Book |
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23 | (3) |
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26 | (3) |
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Chapter 2 Boolean Algebra and Logic Gates |
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29 | (28) |
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2.1 Data Representation and Processing |
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29 | (2) |
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2.2 Basic Logic Operations |
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31 | (4) |
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31 | (1) |
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32 | (1) |
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33 | (2) |
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35 | (2) |
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35 | (1) |
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35 | (1) |
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36 | (1) |
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37 | (2) |
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37 | (1) |
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37 | (1) |
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38 | (1) |
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39 | (4) |
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41 | (2) |
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2.6 Useful Boolean Identities |
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43 | (1) |
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44 | (3) |
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47 | (2) |
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48 | (1) |
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48 | (1) |
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2.9 IEEE Logic Gate Symbols |
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49 | (1) |
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50 | (7) |
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Chapter 3 Combinational Logic Design |
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57 | (44) |
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3.1 Specifying the Problem |
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57 | (2) |
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3.2 Canonical Logic Forms |
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59 | (2) |
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3.2.1 Sum-of-Products (SOP) Form |
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59 | (1) |
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3.2.2 Product-of-Sums (POS) Form |
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60 | (1) |
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3.3 Extracting Canonical Forms |
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61 | (5) |
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3.3.1 Minterms and Maxterms |
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63 | (2) |
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3.3.2 Properties of SOP and POS Forms |
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65 | (1) |
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3.4 The Exclusive-OR and Equivalence Operations |
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66 | (2) |
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68 | (8) |
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69 | (2) |
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71 | (4) |
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3.5.3 Application of Logic Arrays |
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75 | (1) |
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3.6 BCD and 7-Segment Displays |
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76 | (4) |
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80 | (4) |
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3.7.1 2-Variable Karnaugh Maps |
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81 | (3) |
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3.8 3-Variable Karnaugh Maps |
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84 | (5) |
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3.8.1 "Don't Care" Conditions |
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88 | (1) |
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3.8.2 Alternative 3-Variable Map Layout |
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89 | (1) |
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3.9 4-Variable Karnaugh Maps |
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89 | (4) |
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3.10 The Role of the Logic Designer |
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93 | (1) |
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94 | (7) |
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Chapter 4 Digital Hardware |
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101 | (42) |
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4.1 Voltages as Logic Variables |
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101 | (3) |
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103 | (1) |
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4.2 Digital Integrated Circuits |
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104 | (5) |
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108 | (1) |
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109 | (10) |
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4.3.1 Output Switching Times |
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110 | (1) |
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4.3.2 The Propagation Delay |
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111 | (1) |
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112 | (3) |
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4.3.4 Extension to Other Logic Gates |
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115 | (1) |
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116 | (3) |
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4.4 Basic Electric Circuits |
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119 | (9) |
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120 | (2) |
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122 | (1) |
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123 | (5) |
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4.4.4 Application to Digital Circuits |
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128 | (1) |
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128 | (4) |
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130 | (1) |
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4.5.2 Electromagnetic Interference |
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131 | (1) |
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132 | (3) |
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133 | (1) |
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4.6.2 TTL Integrated Circuits |
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133 | (1) |
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4.6.3 Emitter-Coupled Logic (ECL) |
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134 | (1) |
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4.7 The Hardware Designer |
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135 | (1) |
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135 | (8) |
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Chapter 5 First Concepts in VHDL |
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143 | (34) |
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143 | (2) |
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144 | (1) |
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5.1.2 Using a Hardware Description Language |
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145 | (1) |
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5.2 Defining Modules in VHDL |
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145 | (13) |
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5.2.1 Concurrent Operations |
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152 | (3) |
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155 | (1) |
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156 | (2) |
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158 | (5) |
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163 | (4) |
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167 | (2) |
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169 | (2) |
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171 | (1) |
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172 | (5) |
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Chapter 6 CMOS Logic Circuits |
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177 | (42) |
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177 | (1) |
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6.2 Electronic Logic Gates |
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178 | (1) |
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179 | (4) |
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6.4 The NOT Function in CMOS |
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183 | (4) |
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6.4.1 Complementary Pairs |
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185 | (1) |
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186 | (1) |
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6.5 Logic Formation Using MOSFETs |
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187 | (8) |
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190 | (2) |
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192 | (1) |
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6.5.3 The CMOS-Logic Connection |
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193 | (2) |
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6.6 Complex Logic Gates in CMOS |
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195 | (7) |
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6.6.1 3-Input Logic Gates |
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196 | (3) |
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6.6.2 A General 4-Input Gate |
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199 | (2) |
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201 | (1) |
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6.7 MOSFET Logic Formalism |
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202 | (10) |
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6.7.1 FET Logic Descriptions |
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203 | (1) |
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6.7.2 Voltage Transmission Characteristics |
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204 | (2) |
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6.7.3 The Complementary Principle |
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206 | (2) |
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208 | (2) |
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6.7.5 Fiber-Optic Transmission Networks |
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210 | (2) |
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212 | (7) |
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Chapter 7 Silicon Chips and VLSI |
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219 | (56) |
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7.1 What Is VLSI Engineering? |
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219 | (7) |
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7.1.1 Inside a Computer Chip |
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220 | (1) |
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220 | (4) |
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224 | (1) |
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225 | (1) |
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7.2 Lithography and Patterning |
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226 | (4) |
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7.2.1 The Importance of Physical Layout |
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229 | (1) |
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230 | (14) |
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232 | (5) |
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237 | (3) |
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7.3.3 MOSFET Design Rules |
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240 | (1) |
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7.3.4 The Incredible Shrinking Transistor |
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241 | (3) |
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244 | (10) |
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245 | (1) |
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7.4.2 Electrical Modeling |
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246 | (8) |
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7.5 MOSFET Arrays and AOI Gates |
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254 | (5) |
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254 | (2) |
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7.5.2 NAND and NOR Layout |
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256 | (1) |
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7.5.3 Complex Logic Gates |
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257 | (1) |
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7.5.4 General Observations |
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258 | (1) |
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7.6 Cells, Libraries, and Hierarchical Design |
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259 | (5) |
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7.6.1 Creation of a Cell Library |
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260 | (2) |
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262 | (1) |
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262 | (2) |
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7.7 Floorplans and Interconnect Wiring |
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264 | (6) |
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266 | (2) |
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268 | (2) |
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270 | (5) |
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Chapter 8 Logic Components |
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275 | (52) |
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8.1 Concept of a Digital Component |
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275 | (1) |
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276 | (2) |
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8.3 BCD Validity Detector |
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278 | (2) |
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280 | (3) |
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283 | (6) |
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8.5.1 Multiplexors as Logic Elements |
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286 | (2) |
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288 | (1) |
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289 | (3) |
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290 | (1) |
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8.6.2 Multiplexed Transmission System |
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291 | (1) |
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292 | (9) |
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293 | (1) |
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294 | (1) |
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294 | (2) |
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296 | (2) |
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298 | (2) |
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8.7.6 CMOS Adder Circuits |
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300 | (1) |
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301 | (10) |
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8.8.1 Subtractor Logic Circuits |
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307 | (1) |
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308 | (3) |
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311 | (3) |
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8.10 Transmission Gate Logic |
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314 | (5) |
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8.10.1 Transmission Gate Multiplexors |
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315 | (2) |
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8.10.2 TG XOR and XNOR Gates |
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317 | (1) |
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8.10.3 CMOS Transmission Gates |
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318 | (1) |
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319 | (1) |
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320 | (7) |
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Chapter 9 Memory Elements and Arrays |
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327 | (48) |
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327 | (1) |
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328 | (4) |
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328 | (3) |
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331 | (1) |
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9.3 Clocks and Synchronization |
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332 | (2) |
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333 | (1) |
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334 | (1) |
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9.4 Master-Slave and Edge-Triggered Flip-Flops |
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334 | (9) |
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9.4.1 A Master-Slave D-Type Flip-Flop |
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335 | (6) |
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9.4.2 Other Types of Flip-Flops |
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341 | (2) |
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343 | (5) |
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9.5.1 Basic Storage Register |
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343 | (1) |
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344 | (4) |
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9.6 Random-Access Memory (RAM) |
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348 | (8) |
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348 | (2) |
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350 | (3) |
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353 | (1) |
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9.6.4 Parity and Error-Detection Codes |
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354 | (2) |
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9.7 Read-Only Memory (ROM) |
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356 | (1) |
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356 | (6) |
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362 | (5) |
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362 | (1) |
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363 | (3) |
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366 | (1) |
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9.10 Transmission-Gate Circuits |
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367 | (3) |
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367 | (2) |
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369 | (1) |
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370 | (5) |
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Chapter 10 Sequential Logic Networks |
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375 | (28) |
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10.1 The Concept of a Sequential Network |
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375 | (5) |
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10.1.1 Sequential Network Requirements |
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377 | (2) |
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10.1.2 A General Sequential Network |
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379 | (1) |
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10.2 Analysis of Sequential Networks |
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380 | (9) |
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10.2.1 Single-State Variable Circuits |
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381 | (5) |
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10.2.2 Multi-State Variable Networks |
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386 | (3) |
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10.2.3 General Characteristics |
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389 | (1) |
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10.3 Sequential Network Design |
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389 | (2) |
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391 | (6) |
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10.5 The Importance of State Machines |
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397 | (1) |
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397 | (6) |
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Chapter 11 Computer Basics |
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403 | (48) |
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11.1 An Overview of Computer Operations |
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403 | (6) |
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11.1.1 Major Components of a Computer |
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404 | (1) |
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11.1.2 What Can a Computer Do? |
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405 | (1) |
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11.1.3 The von Neumann Model |
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405 | (2) |
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407 | (2) |
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11.1.5 Computer Registers |
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409 | (1) |
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11.2 The Central Processor Unit: A First Look |
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409 | (6) |
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11.2.1 The Instruction Fetch Network |
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410 | (2) |
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11.2.2 Concept of the Datapath |
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412 | (1) |
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11.2.3 Datapath Operations |
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413 | (2) |
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415 | (8) |
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416 | (2) |
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11.3.2 The Arithmetic and Logic Unit |
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418 | (5) |
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423 | (1) |
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11.4 Instructions and the Datapath |
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423 | (8) |
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431 | (4) |
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11.6 CISC and RISC Architectures |
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435 | (5) |
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11.6.1 CISC and Microprogramming |
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436 | (1) |
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437 | (3) |
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440 | (1) |
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11.7 Floating-Point Operations |
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440 | (4) |
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11.7.1 Arithmetic Operations |
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442 | (1) |
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11.7.2 Application to Computers |
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443 | (1) |
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11.8 VLSI Aspects of Computer Design |
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444 | (2) |
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446 | (5) |
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Chapter 12 Advanced Computer Concepts |
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451 | (40) |
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451 | (1) |
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452 | (9) |
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457 | (3) |
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460 | (1) |
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461 | (7) |
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12.3.1 VLSI Aspects of Cache Memory |
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464 | (4) |
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12.4 Superscalar Architectures |
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468 | (2) |
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12.5 Basic Concepts of Parallel Computing |
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470 | (16) |
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12.5.1 Classifications of Parallel Machines |
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473 | (2) |
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12.5.2 Examples of Parallel Computations |
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475 | (4) |
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12.5.3 General Architectures |
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479 | (2) |
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12.5.4 General Design Variables |
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481 | (1) |
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12.5.5 Interconnection Networks |
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482 | (2) |
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12.5.6 The Challenge of Parallel Computing |
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484 | (1) |
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12.5.7 Optical Interconnects |
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484 | (2) |
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486 | (3) |
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489 | (2) |
Epilog |
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491 | (2) |
Index |
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493 | |