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First Course in Digital Systems Design: An Integrated Approach [Kõva köide]

  • Formaat: Hardback, 516 pages, kõrgus x laius x paksus: 254x208x23 mm, kaal: 1135 g, Illustrations
  • Ilmumisaeg: 16-Apr-1999
  • Kirjastus: Nelson Engineering
  • ISBN-10: 0534934129
  • ISBN-13: 9780534934125
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  • Formaat: Hardback, 516 pages, kõrgus x laius x paksus: 254x208x23 mm, kaal: 1135 g, Illustrations
  • Ilmumisaeg: 16-Apr-1999
  • Kirjastus: Nelson Engineering
  • ISBN-10: 0534934129
  • ISBN-13: 9780534934125
This textbook for electrical engineering, computer engineering, and computer science students integrates modern technology into the discussion of classical topics. Includes chapters on Boolean algebra, VHDL, CMOS, VLSI, RISC architectures, and parallel computing. Annotation c. by Book News, Inc., Portland, Or.

This book provides a new paradigm for teaching digital systems design. It puts forth the view that modern digital logic consists of several interacting areas that combine in a cohesive fashion. This includes traditional subjects such as Boolean algebra, logic formalisms, Karnaugh maps, and other classical topics. However, it goes beyond these subject areas by including VHDL, CMOS, VLSI and RISC architectures to show what the field looks like to a modern logic designer. Modern digital design is no longer practiced as a stand-alone art. The integrated approach used in this book is designed to ensure that graduating engineers are prepared to meet the challenges of the new century.
Chapter 1 Concepts in Digital Systems
1(28)
1.1 What Is a Digital System?
1(1)
1.2 Views of a Digital System
2(2)
1.2.1 Hierarchies
2(1)
1.2.2 The Personal Computer
3(1)
1.3 Introduction to Binary Numbers
4(2)
1.4 Data Representations
6(2)
1.5 Binary and Decimal Numbers
8(7)
1.5.1 Binary-to-Decimal Conversion
8(2)
1.5.2 Decimal-to-Binary Conversion
10(2)
1.5.3 Fractions
12(2)
1.5.4 Hexadecimal Numbers
14(1)
1.6 Cells and Hierarchy
15(4)
1.7 System Primitives
19(3)
1.8 Metrics
22(1)
1.9 Hierarchical Plan for the Book
23(3)
1.10 Problems
26(3)
Chapter 2 Boolean Algebra and Logic Gates
29(28)
2.1 Data Representation and Processing
29(2)
2.2 Basic Logic Operations
31(4)
2.2.1 The NOT Operation
31(1)
2.2.2 The OR Gate
32(1)
2.2.3 The AND Gate
33(2)
2.3 Basic Identities
35(2)
2.3.1 NOT Identity
35(1)
2.3.2 OR Identities
35(1)
2.3.3 AND Identities
36(1)
2.4 Algebraic Laws
37(2)
2.4.1 Commutative Laws
37(1)
2.4.2 Associative Laws
37(1)
2.4.3 Distributive Laws
38(1)
2.5 NOR and NAND Gates
39(4)
2.5.1 DeMorgan Theorems
41(2)
2.6 Useful Boolean Identities
43(1)
2.7 Algebraic Reductions
44(3)
2.8 Complete Logic Sets
47(2)
2.8.1 NAND-Based Logic
48(1)
2.8.2 NOR-Based Logic
48(1)
2.9 IEEE Logic Gate Symbols
49(1)
2.10 Problems
50(7)
Chapter 3 Combinational Logic Design
57(44)
3.1 Specifying the Problem
57(2)
3.2 Canonical Logic Forms
59(2)
3.2.1 Sum-of-Products (SOP) Form
59(1)
3.2.2 Product-of-Sums (POS) Form
60(1)
3.3 Extracting Canonical Forms
61(5)
3.3.1 Minterms and Maxterms
63(2)
3.3.2 Properties of SOP and POS Forms
65(1)
3.4 The Exclusive-OR and Equivalence Operations
66(2)
3.5 Logic Arrays
68(8)
3.5.1 AND and OR Arrays
69(2)
3.5.2 SOP and POS Arrays
71(4)
3.5.3 Application of Logic Arrays
75(1)
3.6 BCD and 7-Segment Displays
76(4)
3.7 Karnaugh Maps
80(4)
3.7.1 2-Variable Karnaugh Maps
81(3)
3.8 3-Variable Karnaugh Maps
84(5)
3.8.1 "Don't Care" Conditions
88(1)
3.8.2 Alternative 3-Variable Map Layout
89(1)
3.9 4-Variable Karnaugh Maps
89(4)
3.10 The Role of the Logic Designer
93(1)
3.11 Problems
94(7)
Chapter 4 Digital Hardware
101(42)
4.1 Voltages as Logic Variables
101(3)
4.1.1 Logic Levels
103(1)
4.2 Digital Integrated Circuits
104(5)
4.2.1 Integration Levels
108(1)
4.3 Logic Delay Times
109(10)
4.3.1 Output Switching Times
110(1)
4.3.2 The Propagation Delay
111(1)
4.3.3 Fan-Out and Fan-In
112(3)
4.3.4 Extension to Other Logic Gates
115(1)
4.3.5 Logic Cascades
116(3)
4.4 Basic Electric Circuits
119(9)
4.4.1 Resistance
120(2)
4.4.2 Capacitance
122(1)
4.4.3 The RC Circuit
123(5)
4.4.4 Application to Digital Circuits
128(1)
4.5 Transmission Lines
128(4)
4.5.1 Crosstalk
130(1)
4.5.2 Electromagnetic Interference
131(1)
4.6 Logic Families
132(3)
4.6.1 CMOS
133(1)
4.6.2 TTL Integrated Circuits
133(1)
4.6.3 Emitter-Coupled Logic (ECL)
134(1)
4.7 The Hardware Designer
135(1)
4.8 Problems
135(8)
Chapter 5 First Concepts in VHDL
143(34)
5.1 Introduction
143(2)
5.1.1 Basic Concepts
144(1)
5.1.2 Using a Hardware Description Language
145(1)
5.2 Defining Modules in VHDL
145(13)
5.2.1 Concurrent Operations
152(3)
5.2.2 Identifiers
155(1)
5.2.3 Propagation Delay
156(2)
5.3 Structural Modeling
158(5)
5.4 Conditional Models
163(4)
5.5 Binary Words
167(2)
5.6 Libraries
169(2)
5.7 Learning VHDL
171(1)
5.8 Problems
172(5)
Chapter 6 CMOS Logic Circuits
177(42)
6.1 CMOS Electronics
177(1)
6.2 Electronic Logic Gates
178(1)
6.3 MOSFETs
179(4)
6.4 The NOT Function in CMOS
183(4)
6.4.1 Complementary Pairs
185(1)
6.4.2 The CMOS Inverter
186(1)
6.5 Logic Formation Using MOSFETs
187(8)
6.5.1 The NOR Gate
190(2)
6.5.2 The NAND Gate
192(1)
6.5.3 The CMOS-Logic Connection
193(2)
6.6 Complex Logic Gates in CMOS
195(7)
6.6.1 3-Input Logic Gates
196(3)
6.6.2 A General 4-Input Gate
199(2)
6.6.3 Logic Cascades
201(1)
6.7 MOSFET Logic Formalism
202(10)
6.7.1 FET Logic Descriptions
203(1)
6.7.2 Voltage Transmission Characteristics
204(2)
6.7.3 The Complementary Principle
206(2)
6.7.4 Current Switching
208(2)
6.7.5 Fiber-Optic Transmission Networks
210(2)
6.8 Problems
212(7)
Chapter 7 Silicon Chips and VLSI
219(56)
7.1 What Is VLSI Engineering?
219(7)
7.1.1 Inside a Computer Chip
220(1)
7.1.2 A Silicon Primer
220(4)
7.1.3 The pn Junction
224(1)
7.1.4 Silicon Devices
225(1)
7.2 Lithography and Patterning
226(4)
7.2.1 The Importance of Physical Layout
229(1)
7.3 MOSFETs
230(14)
7.3.1 MOSFET Switching
232(5)
7.3.2 pFETs
237(3)
7.3.3 MOSFET Design Rules
240(1)
7.3.4 The Incredible Shrinking Transistor
241(3)
7.4 Basic Circuit Layout
244(10)
7.4.1 The CMOS Inverter
245(1)
7.4.2 Electrical Modeling
246(8)
7.5 MOSFET Arrays and AOI Gates
254(5)
7.5.1 Wiring Strategies
254(2)
7.5.2 NAND and NOR Layout
256(1)
7.5.3 Complex Logic Gates
257(1)
7.5.4 General Observations
258(1)
7.6 Cells, Libraries, and Hierarchical Design
259(5)
7.6.1 Creation of a Cell Library
260(2)
7.6.2 Cell Placement
262(1)
7.6.3 System Hierarchies
262(2)
7.7 Floorplans and Interconnect Wiring
264(6)
7.7.1 Interconnects
266(2)
7.7.2 Wiring Delays
268(2)
7.8 Problems
270(5)
Chapter 8 Logic Components
275(52)
8.1 Concept of a Digital Component
275(1)
8.2 An Equality Detector
276(2)
8.3 BCD Validity Detector
278(2)
8.4 Line Decoders
280(3)
8.5 Multiplexors
283(6)
8.5.1 Multiplexors as Logic Elements
286(2)
8.5.2 VHDL Description
288(1)
8.6 Demultiplexors
289(3)
8.6.1 VHDL Description
290(1)
8.6.2 Multiplexed Transmission System
291(1)
8.7 Binary Adders
292(9)
8.7.1 The Full-Adder
293(1)
8.7.2 Half-Adders
294(1)
8.7.3 Adder Circuits
294(2)
8.7.4 VHDL Descriptions
296(2)
8.7.5 Parallel Adders
298(2)
8.7.6 CMOS Adder Circuits
300(1)
8.8 Subtraction
301(10)
8.8.1 Subtractor Logic Circuits
307(1)
8.8.2 Negative Numbers
308(3)
8.9 Multiplication
311(3)
8.10 Transmission Gate Logic
314(5)
8.10.1 Transmission Gate Multiplexors
315(2)
8.10.2 TG XOR and XNOR Gates
317(1)
8.10.3 CMOS Transmission Gates
318(1)
8.11 Summary
319(1)
8.12 Problems
320(7)
Chapter 9 Memory Elements and Arrays
327(48)
9.1 General Properties
327(1)
9.2 Latches
328(4)
9.2.1 The SR Latch
328(3)
9.2.2 D Latch
331(1)
9.3 Clocks and Synchronization
332(2)
9.3.1 Clocked SR Latch
333(1)
9.3.2 The D Latch
334(1)
9.4 Master-Slave and Edge-Triggered Flip-Flops
334(9)
9.4.1 A Master-Slave D-Type Flip-Flop
335(6)
9.4.2 Other Types of Flip-Flops
341(2)
9.5 Registers
343(5)
9.5.1 Basic Storage Register
343(1)
9.5.2 Shift Registers
344(4)
9.6 Random-Access Memory (RAM)
348(8)
9.6.1 Static RAM Cell
348(2)
9.6.2 SRAM Array
350(3)
9.6.3 Dynamic RAM
353(1)
9.6.4 Parity and Error-Detection Codes
354(2)
9.7 Read-Only Memory (ROM)
356(1)
9.8 CD ROM
356(6)
9.9 CMOS Memories
362(5)
9.9.1 CMOS SRAMs
362(1)
9.9.2 Dynamic RAM
363(3)
9.9.3 ROMs
366(1)
9.10 Transmission-Gate Circuits
367(3)
9.10.1 Basic Latch
367(2)
9.10.2 TG Flip-Flop
369(1)
9.11 Problems
370(5)
Chapter 10 Sequential Logic Networks
375(28)
10.1 The Concept of a Sequential Network
375(5)
10.1.1 Sequential Network Requirements
377(2)
10.1.2 A General Sequential Network
379(1)
10.2 Analysis of Sequential Networks
380(9)
10.2.1 Single-State Variable Circuits
381(5)
10.2.2 Multi-State Variable Networks
386(3)
10.2.3 General Characteristics
389(1)
10.3 Sequential Network Design
389(2)
10.4 Binary Counters
391(6)
10.5 The Importance of State Machines
397(1)
10.6 Problems
397(6)
Chapter 11 Computer Basics
403(48)
11.1 An Overview of Computer Operations
403(6)
11.1.1 Major Components of a Computer
404(1)
11.1.2 What Can a Computer Do?
405(1)
11.1.3 The von Neumann Model
405(2)
11.1.4 Programming
407(2)
11.1.5 Computer Registers
409(1)
11.2 The Central Processor Unit: A First Look
409(6)
11.2.1 The Instruction Fetch Network
410(2)
11.2.2 Concept of the Datapath
412(1)
11.2.3 Datapath Operations
413(2)
11.3 Datapath Components
415(8)
11.3.1 The Register File
416(2)
11.3.2 The Arithmetic and Logic Unit
418(5)
11.3.3 The Local Memory
423(1)
11.4 Instructions and the Datapath
423(8)
11.5 The Control Unit
431(4)
11.6 CISC and RISC Architectures
435(5)
11.6.1 CISC and Microprogramming
436(1)
11.6.2 RISC Machines
437(3)
11.6.3 Modern Computers
440(1)
11.7 Floating-Point Operations
440(4)
11.7.1 Arithmetic Operations
442(1)
11.7.2 Application to Computers
443(1)
11.8 VLSI Aspects of Computer Design
444(2)
11.9 Problems
446(5)
Chapter 12 Advanced Computer Concepts
451(40)
12.1 Computing Speed
451(1)
12.2 Pipelining
452(9)
12.2.1 Data Hazards
457(3)
12.2.2 Resolving Hazards
460(1)
12.3 Cache Memory
461(7)
12.3.1 VLSI Aspects of Cache Memory
464(4)
12.4 Superscalar Architectures
468(2)
12.5 Basic Concepts of Parallel Computing
470(16)
12.5.1 Classifications of Parallel Machines
473(2)
12.5.2 Examples of Parallel Computations
475(4)
12.5.3 General Architectures
479(2)
12.5.4 General Design Variables
481(1)
12.5.5 Interconnection Networks
482(2)
12.5.6 The Challenge of Parallel Computing
484(1)
12.5.7 Optical Interconnects
484(2)
12.6 Problems
486(3)
12.7 References
489(2)
Epilog 491(2)
Index 493