Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes.
New sections cover advanced techniques, and a new chapter, The Road To Formal Signoff, emphasizes techniques used when replacing simulation work with Formal Verification. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity.
- Covers formal verification algorithms that help users gain full coverage without exhaustive simulation
- Helps readers understand formal verification tools and how they differ from simulation tools
- Shows how to create instant test benches to gain insights into how models work and to find initial bugs
- Presents insights from Intel insiders who share their hard-won knowledge and solutions to complex design problems
Formal verification: from dreams to reality
Basic formal verification algorithms
Introduction to SystemVerilog Assertions
Formal property verification
Effective formal property verification for design exercise
Effective FPV for verification
Formal property verification apps for specific problems
Formal equivalence verification
Formal verifications greatest bloopers: the danger of false positives
Dealing with complexity
Formal signoff on real projects
Your new FV-aware lifestyle
Erik Seligman is currently a Senior Product Engineering Architect at Cadence Design Systems, where he helps to plan and support the Jasper Formal Verification tool suite. Previously he worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. In his spare time he hosts the Math Mutation” podcast, and has served as an elected director on the Hillsboro school board. Tom Schubert, now retired, is an Adjunct Professor for the Department of Electrical and Computer Engineering at Portland State University and for eight years had directed the graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intels largest pre-silicon formal verification team, and developed and applied FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis. M. V. Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at Intel and leads the companys Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 20 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation, and various levels of validation including formal verification.
