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FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC 2nd edition [Kõva köide]

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  • Formaat: Hardback, 632 pages, kõrgus x laius x paksus: 257x180x38 mm, kaal: 1270 g
  • Ilmumisaeg: 29-Dec-2017
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 1119282748
  • ISBN-13: 9781119282747
Teised raamatud teemal:
FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC 2nd editionSuurem pilt
  • Formaat: Hardback, 632 pages, kõrgus x laius x paksus: 257x180x38 mm, kaal: 1270 g
  • Ilmumisaeg: 29-Dec-2017
  • Kirjastus: John Wiley & Sons Inc
  • ISBN-10: 1119282748
  • ISBN-13: 9781119282747
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781119282747.html
Märksõnad:

A hands-on introduction to FPGA prototyping and SoC design

This Second Edition of the popular book follows the same “learning-by-doing” approach to teach the fundamentals and practices of VHDL synthesis and FPGA prototyping. It uses a coherent series of examples to demonstrate the process to develop sophisticated digital circuits and IP (intellectual property) cores, integrate them into an SoC (system on a chip) framework, realize the system on an FPGA prototyping board, and verify the hardware and software operation. The examples start with simple gate-level circuits, progress gradually through the RT (register transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. Although it is an introductory text, the examples are developed in a rigorous manner, and the derivations follow strict design guidelines and coding practices used for large, complex digital systems.

The new edition is completely updated. It presents the hardware design in the SoC context and introduces the hardware-software co-design concept. Instead of treating examples as isolated entities, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software “programmability” and develop complex and interesting embedded system projects. The revised edition:

  • Adds four general-purpose IP cores, which are multi-channel PWM (pulse width modulation) controller, I2C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
  • Introduces a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelop generator.
  • Expands the original video controller into a complete stream-based video subsystem that incorporates a video synchronization circuit, a test pattern generator, an OSD (on-screen display) controller, a sprite generator, and a frame buffer.
  • Introduces basic concepts of software-hardware co-design with Xilinx MicroBlaze MCS soft-core processor.
  • Provides an overview of bus interconnect and interface circuit.
  • Introduces basic embedded system software development.
  • Suggests additional modules and peripherals for interesting and challenging projects.

The FPGA Prototyping by VHDL Examples, Second Edition makes a natural companion text for introductory and advanced digital design courses and embedded system course. It also serves as an ideal self-teaching guide for practicing engineers who wish to learn more about this emerging area of interest.

Preface xxv
Acknowledgments xxxi
PART I BASIC DIGITAL CIRCUITS DEVELOPMENT
1 Gate-Level Combinational Circuit
1(12)
1.1 Overview of VHDL
1(1)
1.2 General description
2(4)
1.2.1 Basic lexical rules
3(1)
1.2.2 Library and package
3(1)
1.2.3 Entity declaration
3(1)
1.2.4 Data type and operators
3(1)
1.2.5 Architecture body
4(1)
1.2.6 Code of a 2-bit comparator
5(1)
1.3 Structural description
6(2)
1.4 Top-level signal mapping
8(1)
1.5 Testbench
9(2)
1.6 Bibliographic notes
11(1)
1.7 Suggested experiments
11(2)
1.7.1 Code for gate-level greater-than circuit
11(1)
1.7.2 Code for gate-level binary decoder
11(2)
2 Overview of FPGA and EDA Software
13(10)
2.1 FPGA
13(2)
2.1.1 Overview of a general FPGA device
13(1)
2.1.2 Overview of the Xilinx Artix-7 devices
14(1)
2.2 Overview of the Digilent Nexys 4 DDR board
15(1)
2.3 Development flow
16(2)
2.4 Xilinx Vivado Design Suite
18(1)
2.5 Bibliographic notes
18(1)
2.6 Suggested experiments
18(5)
2.6.1 Gate-level greater-than circuit
18(2)
2.6.2 Gate-level binary decoder
20(3)
3 RT-Level Combinational Circuit
23(38)
3.1 RT-Level Components
23(6)
3.1.1 Relational operators
25(1)
3.1.2 Arithmetic operators
25(2)
3.1.3 Other synthesis-related VHDL constructs
27(1)
3.1.4 Summary
28(1)
3.2 Routing circuit with concurrent assignment statements
29(5)
3.2.1 Conditional signal assignment statement
29(3)
3.2.2 Selected signal assignment statement
32(2)
3.3 Modeling with a process
34(2)
3.3.1 Process
34(1)
3.3.2 Sequential signal assignment statement
35(1)
3.4 Routing circuit with if and case statements
36(5)
3.4.1 If statement
36(1)
3.4.2 Case statement
37(2)
3.4.3 Comparison to concurrent statements
39(1)
3.4.4 Unintended memory
40(1)
3.5 Constants and generics
41(3)
3.5.1 Constants
41(2)
3.5.2 Generics
43(1)
3.6 Replicated structure
44(2)
3.6.1 Loop statements
44(1)
3.6.2 Example
45(1)
3.7 Design examples
46(12)
3.7.1 Hexadecimal digit to seven-segment LED decoder
46(4)
3.7.2 Sign-magnitude adder
50(3)
3.7.3 Barrel shifter
53(1)
3.7.4 Simplified floating-point adder
54(4)
3.8 Bibliographic notes
58(1)
3.9 Suggested experiments
58(3)
3.9.1 Multi-function barrel shifter
58(1)
3.9.2 Parameterized barrel shifter
58(1)
3.9.3 Dual-priority encoder
59(1)
3.9.4 BCD incrementor
59(1)
3.9.5 Floating-point greater-than circuit
59(1)
3.9.6 Floating-point and signed integer conversion circuit
59(1)
3.9.7 Enhanced floating-point adder
60(1)
4 Regular Sequential Circuit
61(32)
4.1 Introduction
61(3)
4.1.1 D FF and register
62(1)
4.1.2 Basic block system
62(1)
4.1.3 Code development
63(1)
4.1.4 Sequential circuit coding style
63(1)
4.2 HDL code of the FF and register
64(4)
4.2.1 D FF
64(3)
4.2.2 Register
67(1)
4.3 Simple design examples
68(4)
4.3.1 Shift register
68(1)
4.3.2 Binary counter and variant
69(3)
4.4 Testbench for sequential circuits
72(3)
4.5 Case study
75(12)
4.5.1 LED time-multiplexing circuit
76(7)
4.5.2 Stopwatch
83(4)
4.6 Timing and clocking
87(4)
4.6.1 Timing of FF
87(1)
4.6.2 Maximum operating frequency
88(1)
4.6.3 Clock tree
89(1)
4.6.4 GALS system and CDC
90(1)
4.7 Bibliographic notes
91(1)
4.8 Suggested experiments
91(2)
4.8.1 Programmable square wave generator
91(1)
4.8.2 PWM and LED dimmer
91(1)
4.8.3 Rotating square circuit
91(1)
4.8.4 Heartbeat circuit
92(1)
4.8.5 Rotating LED banner circuit
92(1)
4.8.6 Enhanced stopwatch
92(1)
5 FSM
93(20)
5.1 Introduction
93(4)
5.1.1 Mealy and Moore outputs
94(1)
5.1.2 FSM representation
94(3)
5.2 FSM code development
97(3)
5.3 Design examples
100(10)
5.3.1 Rising-edge detector
100(4)
5.3.2 Debouncing circuit
104(4)
5.3.3 Testing circuit
108(2)
5.4 Bibliographic notes
110(1)
5.5 Suggested experiments
110(3)
5.5.1 Dual-edge detector
110(1)
5.5.2 Early detection debouncing circuit
110(1)
5.5.3 Parking lot occupancy counter
110(3)
6 FSMD
113(32)
6.1 Introduction
113(6)
6.1.1 Single RT operation
114(1)
6.1.2 ASMD chart
114(2)
6.1.3 Decision box with a register
116(3)
6.2 Code development of an FSMD
119(6)
6.2.1 Debouncing circuit based on RT methodology
119(1)
6.2.2 Code with explicit data path components
119(3)
6.2.3 Code with implicit data path components
122(1)
6.2.4 Comparison
123(2)
6.3 Design examples
125(16)
6.3.1 Fibonacci number circuit
125(3)
6.3.2 Division circuit
128(3)
6.3.3 Binary-to-BCD conversion circuit
131(3)
6.3.4 Period counter
134(3)
6.3.5 Accurate low-frequency counter
137(4)
6.4 Bibliographic notes
141(1)
6.5 Suggested experiments
141(4)
6.5.1 Early detection debouncing circuit
141(1)
6.5.2 BCD-to-binary conversion circuit
141(1)
6.5.3 Fibonacci circuit with BCD I/O: design approach 1
141(1)
6.5.4 Fibonacci circuit with BCD I/O: design approach 2
142(1)
6.5.5 Auto-scaled low-frequency counter
142(1)
6.5.6 Reaction timer
143(1)
6.5.7 Babbage difference engine emulation circuit
143(2)
7 RAM and Buffer of FPGA
145(26)
7.1 Embedded memory of FPGA device
145(2)
7.1.1 Memory of an Artix device
146(1)
7.1.2 Memory available in a Nexys 4 DDR board
146(1)
7.2 General description for a RAM-like component
147(6)
7.2.1 Register file
147(2)
7.2.2 Dynamic Array Indexing Operation
149(2)
7.2.3 Key aspects of a RAM module
151(1)
7.2.4 Genuine ROM
151(2)
7.3 FIFO buffer
153(5)
7.3.1 FIFO read configuration
153(1)
7.3.2 Circular queue implementation
154(4)
7.4 HDL templates for memory inference
158(6)
7.4.1 Methods to incorporate memory modules
158(1)
7.4.2 Synchronous dual-port RAM
159(1)
7.4.3 "Simple" synchronous dual-port RAM
160(1)
7.4.4 Synchronous single-port RAM
161(1)
7.4.5 Synchronous ROM
162(1)
7.4.6 BRAM-based FIFO buffer
163(1)
7.4.7 Design considerations
164(1)
7.5 Overview of the memory controller
164(2)
7.6 Bibliographic notes
166(1)
7.7 Suggested experiments
166(5)
7.7.1 ROM-based sign-magnitude adder
166(1)
7.7.2 ROM-based temperature conversion
166(1)
7.7.3 FIFO with data width conversion
167(1)
7.7.4 Standard FIFO to FWFT FIFO conversion circuit
167(1)
7.7.5 FIFO buffer with extended status
167(1)
7.7.6 Stack
167(4)
PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM
8 Overview of Embedded SoC Systems
171(16)
8.1 Embedded SoC
171(2)
8.1.1 Overview of embedded systems
171(1)
8.1.2 FPGA-based SoC
172(1)
8.1.3 IP cores
172(1)
8.2 Development flow of the embedded SoC
173(3)
8.2.1 Hardware--software partition
173(1)
8.2.2 Hardware development flow
173(2)
8.2.3 Software development flow
175(1)
8.2.4 Physical implementation and test
175(1)
8.2.5 Custom IP core development
175(1)
8.3 FPro SoC platform
176(4)
8.3.1 Motivations
176(1)
8.3.2 Platform hardware organization
177(2)
8.3.3 Platform software organization
179(1)
8.3.4 Modified development flow
180(1)
8.4 Adaptation on the Digilent Nexys 4 DDR board
180(2)
8.5 Portability
182(2)
8.5.1 Processor module and bridge
182(1)
8.5.2 MMIO subsystem
183(1)
8.5.3 Video subsystem
183(1)
8.6 Organization
184(1)
8.7 Bibliographic notes
184(3)
9 Bare Metal System Software Development
187(26)
9.1 Bare metal system development overview
187(2)
9.1.1 Desktop-like system versus bare metal system
187(1)
9.1.2 Basic embedded program architecture
188(1)
9.2 Memory-mapped I/O
189(2)
9.2.1 Overview
189(1)
9.2.2 Memory alignment
190(1)
9.2.3 I/O register map
190(1)
9.2.4 I/O address space of the FPro system
190(1)
9.3 Direct I/O register access
191(2)
9.3.1 Review of C pointer
191(1)
9.3.2 C pointer for I/O register
192(1)
9.4 Robust I/O register access
193(4)
9.4.1 chu_io_map.h and chu_io_map.vhd
193(1)
9.4.2 inttypes.h
194(1)
9.4.3 chu_io-rw.h
195(2)
9.5 Techniques for low-level I/O operations
197(2)
9.5.1 Bit manipulation
197(1)
9.5.2 Packing and unpacking
198(1)
9.6 Device drivers
199(5)
9.6.1 Overview
199(1)
9.6.2 GPO and GPI drivers
199(2)
9.6.3 Timer driver
201(2)
9.6.4 UART driver
203(1)
9.7 FPro utility routines and directory structure
204(3)
9.7.1 Minimal hardware requirements
204(1)
9.7.2 Utility routines
204(3)
9.7.3 Directory structure
207(1)
9.8 Test program
207(4)
9.8.1 IP core verification routine
207(1)
9.8.2 Programming with limited memory
208(1)
9.8.3 Test function integration
208(1)
9.8.4 Test program for the vanilla FPro system
209(1)
9.8.5 Implementation
210(1)
9.9 Bibliographic notes
211(1)
9.10 Suggested experiments
211(2)
9.10.1 Chasing LEDs
211(1)
9.10.2 Collision LEDs
211(1)
9.10.3 Pulse width modulation
212(1)
9.10.4 System time display
212(1)
10 FPro Bus Protocol and MMIO Slot Specification
213(32)
10.1 FPro bus
213(3)
10.1.1 Overview of the bus
213(1)
10.1.2 SoC interconnect
214(1)
10.1.3 FPro bus protocol specification
215(1)
10.2 Interface with the bus
216(6)
10.2.1 Introduction
216(1)
10.2.2 Write interface and decoding
217(2)
10.2.3 Read interface and multiplexing
219(1)
10.2.4 FIFO buffer as an I/O register
220(1)
10.2.5 Timing consideration
221(1)
10.3 MMIO I/O core
222(5)
10.3.1 MMIO slot interface specification
222(2)
10.3.2 Basic MMIO I/O core construction
224(1)
10.3.3 GPO and GPI cores
225(2)
10.4 Timer core development
227(2)
10.4.1 Custom logic
227(1)
10.4.2 Register map
227(1)
10.4.3 Wrapping circuit for the slot interface
228(1)
10.5 MMIO controller
229(6)
10.5.1 chu_io_map.vhd file
229(2)
10.5.2 HDL code
231(1)
10.5.3 Vanilla MMIO subsystem
232(3)
10.6 MCS I/O bus and bridge
235(3)
10.6.1 Overview of Xilinx MicroBlaze MCS
235(1)
10.6.2 MicroBlaze MCS I/O bus
235(2)
10.6.3 MCS-to-FPro bridge
237(1)
10.7 Vanilla FPro system construction
238(2)
10.8 Bibliographic notes
240(1)
10.9 Suggested experiments
241(4)
10.9.1 FPro bus with a byte-lane enable signal
241(1)
10.9.2 Seven-segment control with a GPO core
241(1)
10.9.3 GPIO core
241(1)
10.9.4 Blinking-LED core
242(1)
10.9.5 Timer core with a programmable period
242(1)
10.9.6 Timer core with a run-once mode
242(3)
11 UART Core
245(28)
11.1 Introduction
245(2)
11.1.1 Overview of serial communication
245(1)
11.1.2 Overview of UART
246(1)
11.1.3 Oversampling procedure
246(1)
11.2 UART Construction
247(8)
11.2.1 Conceptual design
247(1)
11.2.2 Baud rate generator
248(1)
11.2.3 UART receiver
249(3)
11.2.4 UART transmitter
252(2)
11.2.5 Top-level HDL codes
254(1)
11.3 UART core development
255(3)
11.3.1 Register map
256(1)
11.3.2 Wrapping circuit for the slot interface
256(2)
11.4 UART driver
258(6)
11.4.1 Class definition
258(1)
11.4.2 Basic methods
259(1)
11.4.3 ASCII code
260(1)
11.4.4 Display methods
261(3)
11.4.5 Test
264(1)
11.5 Additional project ideas
264(3)
11.5.1 Original serial port
264(1)
11.5.2 Emulated serial port
265(1)
11.5.3 Direct connection
265(1)
11.5.4 USB-to-UART adaptor
266(1)
11.5.5 Wireless adaptor
266(1)
11.6 Bibliographic notes
267(1)
11.7 Suggested experiments
268(5)
11.7.1 UART-controlled chasing LEDs
268(1)
11.7.2 Alternative read configuration
268(1)
11.7.3 UART controller with a parity bit
268(1)
11.7.4 UART core with an error status
268(1)
11.7.5 Configurable UART core
269(1)
11.7.6 UART core with automatic baud rate detection
269(1)
11.7.7 UART core with enhanced automatic baud rate detection
270(1)
11.7.8 UART core with an automatic baud rate and a parity detection circuit
270(3)
PART III EMBEDDED SOC II: BASIC I/O CORES
12 Xilinx XADC Core
273(24)
12.1 Overview of XADC
273(2)
12.1.1 Block diagram
273(1)
12.1.2 Configuration
274(1)
12.2 XADC core development
275(5)
12.2.1 XADC instantiation
275(1)
12.2.2 Basic wrapping circuit design
276(1)
12.2.3 Register map
277(1)
12.2.4 HDL code
278(2)
12.3 XADC core device driver
280(3)
12.3.1 Class definition
280(1)
12.3.2 Class implementation
281(1)
12.3.3 Testing for the XADC core
282(1)
12.4 Sampler FPro system
283(10)
12.4.1 Testing procedure of an FPro core
283(1)
12.4.2 System configuration
283(1)
12.4.3 Hardware derivation
284(8)
12.4.4 Software verification program
292(1)
12.5 Additional project ideas
293(1)
12.6 Bibliographic notes
294(1)
12.7 Suggested experiments
294(3)
12.7.1 Real-time voltage display
294(1)
12.7.2 Potentiometer-controlled chasing LEDs
294(1)
12.7.3 Potentiometer-controlled LED dimmer
295(1)
12.7.4 Enhanced wrapping circuit I
295(1)
12.7.5 Enhanced wrapping circuit II
295(2)
13 Pulse Width Modulation Core
297(12)
13.1 Introduction
297(1)
13.1.1 PWM as analog output
297(1)
13.1.2 Main characteristics
298(1)
13.2 PWM design
298(3)
13.2.1 Basic design
298(2)
13.2.2 Enhanced design
300(1)
13.3 PWM core development
301(3)
13.3.1 Register map
301(1)
13.3.2 Wrapped PWM circuit
302(2)
13.4 PWM driver
304(1)
13.4.1 Class definition
304(1)
13.4.2 Class implementation
304(1)
13.5 Testing
305(1)
13.6 Project ideas
306(1)
13.7 Suggested experiments
307(2)
13.7.1 Police dash light
307(1)
13.7.2 Rainbow night light
307(1)
13.7.3 Enhanced PWM core: part I
307(1)
13.7.4 Enhanced PWM core: part II
308(1)
13.7.5 Enhanced GPIO core
308(1)
13.7.6 Servo motor driver
308(1)
14 Debouncing Core and LED-Mux Core
309(16)
14.1 Debouncing core
309(6)
14.1.1 Multi-bit debouncing circuit
309(3)
14.1.2 Register map and the slot wrapping circuit
312(1)
14.1.3 Driver
313(1)
14.1.4 Test
314(1)
14.2 LED-Mux core
315(6)
14.2.1 Eight-digit seven-segment LED display multiplexing circuit
315(1)
14.2.2 Register map and the slot wrapping circuit
316(2)
14.2.3 Driver
318(2)
14.2.4 Test
320(1)
14.3 Project ideas
321(1)
14.4 Suggested experiments
322(3)
14.4.1 Area comparison of two debouncing circuits
322(1)
14.4.2 Enhanced debouncing core: part I
323(1)
14.4.3 Enhanced debouncing core: part II
323(1)
14.4.4 Rotating square pattern revisited
323(1)
14.4.5 Heartbeat pattern revisited
323(1)
14.4.6 Stopwatch
323(1)
14.4.7 Enhanced LED-mux core
323(2)
15 SPI Core
325(24)
15.1 Overview
325(6)
15.1.1 Conceptual architecture
326(1)
15.1.2 Multiple device configuration
326(2)
15.1.3 Basic timing
328(1)
15.1.4 Operation modes
329(1)
15.1.5 Undefined aspects
330(1)
15.2 SPI controller
331(5)
15.2.1 Basic design
331(1)
15.2.2 FSMD construction
332(1)
15.2.3 HDL implementation
332(4)
15.3 SPI core development
336(2)
15.3.1 Register map
336(1)
15.3.2 Wrapping circuit for the slot interface
336(2)
15.4 SPI Driver
338(2)
15.4.1 Class definition
338(1)
15.4.2 Class implementation
339(1)
15.5 Test
340(3)
15.5.1 ADXL362 accelerometer
341(1)
15.5.2 Test program
342(1)
15.6 Project ideas
343(1)
15.6.1 SD card
343(1)
15.6.2 TFT LCD module
343(1)
15.7 Bibliographic notes
344(1)
15.8 Suggested experiments
344(5)
15.8.1 Inclination sensing
344(1)
15.8.2 "Tapping" detection
345(1)
15.8.3 ADXL362 C++ class
345(1)
15.8.4 Enhanced SPI controller: part I
345(1)
15.8.5 Enhanced SPI controller: part II
345(1)
15.8.6 Automatic-read ADXL362 wrapper: part I
346(1)
15.8.7 Automatic-read ADXL362 wrapper: part II
346(1)
15.8.8 Flash memory access
346(1)
15.8.9 SPI slave controller: part I
346(1)
15.8.10 SPI slave controller: part II
347(2)
16 I2C Core
349(24)
16.1 Overview
349(4)
16.1.1 Electrical characteristics
350(1)
16.1.2 Basic bus protocol
350(1)
16.1.3 Basic timing
351(1)
16.1.4 Additional features
352(1)
16.2 I2C controller
353(9)
16.2.1 Basic design
353(1)
16.2.2 Conceptual FSMD construction
353(3)
16.2.3 Output control logic
356(1)
16.2.4 I2C bus clock generation
356(1)
16.2.5 HDL implementation
357(5)
16.3 I2C core development
362(2)
16.3.1 Register map
362(1)
16.3.2 Wrapping circuit for the slot interface
362(2)
16.4 I2C driver
364(3)
16.4.1 Class definition
364(1)
16.4.2 Class implementation
364(3)
16.5 Test
367(2)
16.5.1 ADT7420 temperature sensor
367(1)
16.5.2 Test program
368(1)
16.6 Project idea
369(1)
16.7 Bibliographic notes
369(1)
16.8 Suggested experiments
370(3)
16.8.1 Thermometer
370(1)
16.8.2 ADT7420 C++ class
370(1)
16.8.3 Enhanced I2C core
370(1)
16.8.4 Automatic-read ADT7420 wrapper
370(1)
16.8.5 I2C slave controller: part I
371(1)
16.8.6 I2C slave controller: part II
371(2)
17 PS2 Core
373(26)
17.1 Introduction
373(2)
17.1.1 PS2-device-to-host communication protocol and timing
374(1)
17.1.2 Host-to-PS2-device communication protocol and timing
374(1)
17.2 PS2 controller
375(10)
17.2.1 Conceptual design
375(1)
17.2.2 PS2 receiving subsystem
375(4)
17.2.3 PS2 transmitting subsystem
379(5)
17.2.4 Complete PS2 system
384(1)
17.3 PS2 core development
385(2)
17.3.1 Register map
385(1)
17.3.2 Wrapping circuit for the slot interface
385(2)
17.4 PS2 driver
387(8)
17.4.1 Class definition
387(1)
17.4.2 Lower layer methods
387(1)
17.4.3 PS2 initialization routine
388(2)
17.4.4 Keyboard routine
390(3)
17.4.5 Mouse routine
393(2)
17.5 Test
395(1)
17.6 Bibliographic notes
396(1)
17.7 Suggested experiments
396(3)
17.7.1 PS2 receiving subsystem with watchdog timer
396(1)
17.7.2 Keyboard-controlled LED flashing circuit
396(1)
17.7.3 Enhanced keyboard driver routine I
397(1)
17.7.4 Enhanced keyboard driver routine II
397(1)
17.7.5 Remote-mode mouse driver
397(1)
17.7.6 Scroll-wheel mouse driver
397(2)
18 Sound I: DDFS Core
399(20)
18.1 Introduction
399(1)
18.2 Design and implementation
400(3)
18.2.1 Direct synthesis of a digital waveform
400(1)
18.2.2 Direct synthesis of an unmodulated analog waveform
401(1)
18.2.3 Direct synthesis of a modulated analog waveform
402(1)
18.3 Fixed-point arithmetic
403(1)
18.4 DDFS Construction
404(3)
18.5 DAC (digital-to-analog converter)
407(2)
18.5.1 Conceptual design
407(1)
18.5.2 HDL implementation
408(1)
18.6 DDFS core development
409(3)
18.6.1 Register map
409(1)
18.6.2 Wrapping circuit for the slot interface
410(2)
18.7 DDFS driver
412(2)
18.7.1 Class definition
412(1)
18.7.2 Class implementation
412(2)
18.8 Testing
414(1)
18.9 Bibliographic notes
415(1)
18.10 Suggested experiments
415(4)
18.10.1 Quadrature phase carrier generation
416(1)
18.10.2 Reduced-size phase-to-amplitude lookup table
416(1)
18.10.3 Additive harmonic synthesis
416(1)
18.10.4 Simple function generator
416(1)
18.10.5 Arbitrary waveform generator
416(1)
18.10.6 Sample-based synthesis
417(2)
19 Sound II: ADSR Core
419(20)
19.1 Introduction
419(1)
19.2 ADSR envelope generator
420(5)
19.2.1 Conceptual FSMD design
421(1)
19.2.2 ASMD chart
421(2)
19.2.3 HDL implementation
423(2)
19.3 ADSR core development
425(3)
19.3.1 Register map
425(1)
19.3.2 Wrapped ADSR circuit
426(2)
19.4 ADSR driver
428(5)
19.4.1 Class definition
428(1)
19.4.2 Configuration methods
429(2)
19.4.3 calc_note_freq() method
431(1)
19.4.4 play-note () method
432(1)
19.5 Testing
433(1)
19.6 Project idea
434(1)
19.7 Bibliographic notes
435(1)
19.8 Suggested experiments
435(4)
19.8.1 RTTTL music player
435(1)
19.8.2 ADSR envelope testing
435(1)
19.8.3 Pushbutton piano
435(1)
19.8.4 Keyboard piano
435(1)
19.8.5 Keyboard recorder
435(1)
19.8.6 Real-time mode ADSR generator
436(1)
19.8.7 Real-time mode button piano
436(1)
19.8.8 Merged DDFS and ADSR core
436(1)
19.8.9 ADSR core with an automatic play FIFO buffer
436(1)
19.8.10 ADSR core for frequency modulation
436(3)
PART IV EMBEDDED SOC III: VIDEO CORES
20 Introduction to the Video System
439(22)
20.1 Introduction to a video display
439(2)
20.1.1 Conceptual video display
439(1)
20.1.2 VGA interface
440(1)
20.2 Stream interface
441(2)
20.2.1 Random-access interface versus stream interface
441(1)
20.2.2 Flow control of the stream interface
441(2)
20.3 VGA synchronization
443(9)
20.3.1 Basic operation of a CRT monitor
443(1)
20.3.2 Horizontal synchronization
444(2)
20.3.3 Vertical synchronization
446(1)
20.3.4 Pixel clock rate
447(1)
20.3.5 VGA synchronization circuit
448(4)
20.4 Bar test-pattern generator
452(2)
20.5 Color-to-grayscale conversion circuit
454(1)
20.6 Demo video system
455(2)
20.7 Advanced video standards
457(1)
20.8 Bibliographic notes
458(1)
20.9 Suggested experiments
458(3)
20.9.1 Horizontal bar test-pattern generator
458(1)
20.9.2 Color channel selection circuit
458(1)
20.9.3 Enhanced color-to-grayscale conversion circuit
458(1)
20.9.4 Square test-pattern generator: part I
458(1)
20.9.5 Square test-pattern generator: part II
459(1)
20.9.6 Square test-pattern generator: part III
459(1)
20.9.7 Square test-pattern generator: part IV
459(2)
21 FPro Video Subsystem
461(40)
21.1 Organization of the video subsystem
461(4)
21.1.1 Overview
461(2)
21.1.2 Video controller
463(1)
21.1.3 HDL of the video controller
464(1)
21.2 FPro video IP core
465(5)
21.2.1 Basic functionality
465(1)
21.2.2 Blending operation
466(2)
21.2.3 Core architecture
468(2)
21.2.4 Alternative core partition
470(1)
21.3 Example video cores
470(5)
21.3.1 Bar test-pattern generator core
470(3)
21.3.2 Color-to-grayscale conversion core
473(1)
21.3.3 "Dummy" core
474(1)
21.4 FPro video synchronization core
475(8)
21.4.1 Line buffer
476(3)
21.4.2 Enhanced video synchronization circuit
479(3)
21.4.3 HDL code
482(1)
21.5 Daisy video subsystem
483(7)
21.5.1 Subsystem overview
483(1)
21.5.2 Interface to the video synchronization core
484(1)
21.5.3 HDL code
485(4)
21.5.4 Timing and performance considerations
489(1)
21.6 Vanilla daisy FPro system
490(4)
21.6.1 Clock management core
490(1)
21.6.2 Updated chu_io_map VHDL package
491(1)
21.6.3 HDL code
491(3)
21.7 Video driver and testing program
494(3)
21.7.1 Updated chu_io_map.h and chu_io_rw.h files
494(1)
21.7.2 GPV core driver
495(1)
21.7.3 Testing program
495(2)
21.8 Bibliographic notes
497(1)
21.9 Suggested experiments
497(4)
21.9.1 Color channel selection core
497(1)
21.9.2 Enhanced color-to-grayscale conversion core
497(1)
21.9.3 Square test-pattern generator core
498(1)
21.9.4 Alpha blending circuit
498(1)
21.9.5 "Highlight" core
498(1)
21.9.6 SVGA synchronization core
498(1)
21.9.7 Configurable video synchronization core
499(1)
21.9.8 Pipelined video subsystem
499(2)
22 Sprite Core
501(22)
22.1 Introduction
501(1)
22.2 Basic design
502(2)
22.2.1 Sprite RAM
502(1)
22.2.2 In-region comparison circuit
503(1)
22.3 Mouse pointer core
504(5)
22.3.1 Pointer sprite RAM
504(1)
22.3.2 Pixel generation circuit
505(2)
22.3.3 Top-level design
507(2)
22.4 "Ghost" character core
509(8)
22.4.1 Multiple images and animation
509(1)
22.4.2 Overview of the palette scheme
510(1)
22.4.3 Ghost sprite RAM and the palette circuit
510(2)
22.4.4 Animation timing circuit
512(1)
22.4.5 Pixel generation circuit
512(3)
22.4.6 Top-level design
515(2)
22.5 Sprite core driver and testing program
517(3)
22.5.1 Sprite core driver
517(1)
22.5.2 Testing program
518(2)
22.6 Bibliographic notes
520(1)
22.7 Suggested experiments
520(3)
22.7.1 Mouse pointer control with a PS2 core
520(1)
22.7.2 Emulated ghost core
520(1)
22.7.3 Palette circuit for the mouse pointer sprite
520(1)
22.7.4 Sprite scaling circuit
520(1)
22.7.5 Portrait mode display
520(1)
22.7.6 Multiple object generation
521(1)
22.7.7 Animation speed control
521(1)
22.7.8 Imitated blinking LED: part I
521(1)
22.7.9 Imitated blinking LED: part II
522(1)
22.7.10 Imitated blinking LED: part III
522(1)
23 On-Screen-Display Core
523(16)
23.1 Introduction to tile graphics
523(2)
23.2 Basic OSD design
525(3)
23.2.1 Text-mode display
525(1)
23.2.2 Font ROM
526(1)
23.2.3 Tile RAM
526(1)
23.2.4 Basic organization
527(1)
23.3 OSD core
528(6)
23.3.1 Font ROM
528(1)
23.3.2 Pixel generation circuit
529(3)
23.3.3 Top-level design
532(2)
23.4 OSD core driver and testing program
534(2)
23.4.1 OSD core driver
534(1)
23.4.2 Testing program
535(1)
23.5 Bibliographic notes
536(1)
23.6 Suggested experiments
536(3)
23.6.1 Rotating banner
536(1)
23.6.2 Text console
536(1)
23.6.3 Underline for the cursor
537(1)
23.6.4 Portrait-mode display
537(1)
23.6.5 Font scaling circuit: part I
537(1)
23.6.6 Font scaling circuit: part II
537(1)
23.6.7 Extended font
537(1)
23.6.8 Tile-based ghost core
538(1)
24 VGA Frame Buffer Core
539(18)
24.1 Overview
539(1)
24.2 Frame buffer core
540(4)
24.2.1 FPGA memory consideration
540(1)
24.2.2 Video memory module
540(2)
24.2.3 Address translation
542(1)
24.2.4 Pixel generation circuit
542(2)
24.3 Register map
544(2)
24.3.1 Top-level HDL code
545(1)
24.4 Driver and the testing program
546(3)
24.4.1 Frame buffer core driver
546(1)
24.4.2 Geometrical modeling
547(2)
24.4.3 Testing program
549(1)
24.5 Project ideas
549(1)
24.6 Bibliographic notes
550(1)
24.7 Suggested experiments
551(6)
24.7.1 Virtual prototyping board panel
551(1)
24.7.2 Virtual analog wall clock
551(1)
24.7.3 Geometrical model functions
551(1)
24.7.4 Simulated "Etch A Sketch" toy
551(1)
24.7.5 Frame buffer core with 3-bit color depth
551(1)
24.7.6 Frame buffer core with 1-bit color depth
552(1)
24.7.7 QVGA frame buffer core
552(1)
24.7.8 Line drawing hardware accelerator
552(1)
24.7.9 Bidirectional frame buffer access: part I
552(1)
24.7.10 Bidirectional frame buffer access: part II
552(5)
PART V EPILOGUE
25 What's Next
557(8)
References
561(4)
Appendix A Tutorials
565(28)
A.1 Overview of the Xilinx Vivado IDE
565(4)
A.2 Short tutorial on Vivado hardware development
569(5)
Appendix A.2.1 Create a design project
570(1)
Appendix A.2.2 Add or create Xilinx IP core instances
571(1)
Appendix A.2.3 Add or create HDL design files
571(1)
Appendix A.2.4 Add a constraint file
572(1)
Appendix A.2.5 Perform synthesis, implementation, and bitstream generation
573(1)
Appendix A.2.6 Program an FPGA device
573(1)
A.3 Short tutorial on Vivado simulation
574(4)
Appendix A.3.1 Add or create an HDL testbench
576(1)
Appendix A.3.2 Perform initial simulation
577(1)
Appendix A.3.3 Customize waveform display
577(1)
A.4 Tutorial on IP instantiation
578(6)
Appendix A.4.1 Dual-clock FIFO core via HDL templates
579(1)
Appendix A.4.2 IP catalog utility
579(1)
Appendix A.4.3 Generate a MicroBlaze MCS component
580(1)
Appendix A.4.4 XADC IP core
581(2)
Appendix A.4.5 Clock management IP core
583(1)
A.5 Short tutorial on FPro system development
584(7)
Appendix A.5.1 Derive FPro system hardware
585(1)
Appendix A.5.2 Export hardware configuration
585(1)
Appendix A.5.3 Derive software
586(4)
Appendix A.5.4 Embed elf file and regenerate bitstream
590(1)
Appendix A.5.5 Set up a terminal emulator program
590(1)
Appendix A.5.6 Program an FPGA device
591(1)
A.6 Bibliographic notes
591(2)
Topic Index 593
PONG P. CHU, PhD is Associate Professor in the Department of Electrical Engineering and Computer Science at Cleveland State University, Cleveland, Ohio. He has taught undergraduate and graduate digital systems and computer architecture courses for more than two decades, and has received multiple instructional grants from the National Science Foundation.