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Fundamentals of Computer Architecture and Design 1st ed. 2017 [Kõva köide]

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  • Formaat: Hardback, 533 pages, kõrgus x laius: 254x178 mm, 45 Tables, black and white; 531 Illustrations, black and white; XIV, 533 p. 531 illus., 1 Hardback
  • Ilmumisaeg: 16-Aug-2017
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319258095
  • ISBN-13: 9783319258096
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Fundamentals of Computer Architecture and Design 1st ed. 2017Suurem pilt
  • Formaat: Hardback, 533 pages, kõrgus x laius: 254x178 mm, 45 Tables, black and white; 531 Illustrations, black and white; XIV, 533 p. 531 illus., 1 Hardback
  • Ilmumisaeg: 16-Aug-2017
  • Kirjastus: Springer International Publishing AG
  • ISBN-10: 3319258095
  • ISBN-13: 9783319258096
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9783319258096.html
Märksõnad:
This textbook provides semester-length coverage of computer architecture and design, providing a strong foundation for students to understand modern computer system architecture and to apply these insights and principles to future computer designs. It is based on the author"s decades of industrial experience with computer architecture and design, as well as with teaching students focused on pursuing careers in computer engineering. Unlike a number of existing textbooks for this course, this one focuses not only on CPU architecture, but also covers in great detail in system buses, peripherals and memories. This book teaches every element in a computing system in two steps. First, it introduces the functionality of each topic (and subtopics) and then goes into "from-scratch design" of a particular digital block from its architectural specifications using timing diagrams. The author describes how the data-path of a certain digital block is generated using timing diagrams, a method wh

ich most textbooks do not cover, but is valuable in actual practice. In the end, the user is ready to use both the design methodology and the basic computing building blocks presented in the book to be able to produce industrial-strength designs.

Review Of Combinational Circuits.- Review Of Sequential Circuits.- Review Of Asynchronous Circuits.- System Bus.- Memory Circuits And Systems.- Central Processing Unit.- System Peripherals.- Special Topics.
1 Review of Combinational Circuits
1(66)
1.1 Logic Gates
2(6)
1.2 Boolean Algebra
8(3)
1.3 Designing Combinational Logic Circuits Using Truth Tables
11(3)
1.4 Combinational Logic Minimization---Karnaugh Maps
14(6)
1.5 Basic Logic Blocks
20(9)
1.6 Combinational Mega Cells
29(38)
2 Review of Sequential Logic Circuits
67(46)
2.1 D Latch
67(2)
2.2 Timing Methodology Using D Latches
69(1)
2.3 D Rip-Flop
70(2)
2.4 Timing Methodology Using D Flip-Flops
72(1)
2.5 Timing Violations
73(6)
2.6 Register
79(1)
2.7 Shift Register
80(1)
2.8 Counter
81(2)
2.9 Moore Machine
83(4)
2.10 Mealy Machine
87(3)
2.11 Controller Design: Moore Machine Versus Counter-Decoder Scheme
90(4)
2.12 Memory
94(3)
2.13 A Design Example Using Sequential Logic and Memory
97(16)
3 Review of Asynchronous Logic Circuits
113(20)
3.1 S-R Latch
113(1)
3.2 Fundamental-Mode Circuit Topology
114(1)
3.3 Fundamental-Mode Asynchronous Logic Circuits
115(8)
3.4 Asynchronous Timing Methodology
123(10)
Reference
131(2)
4 System Bus
133(36)
4.1 Parallel Bus Architectures
133(5)
4.2 Basic Write Transfer
138(2)
4.3 Basic Read Transfer
140(2)
4.4 Bus Master Status Change
142(3)
4.5 Bus Master Handshake
145(1)
4.6 Arbiter
145(3)
4.7 Bus Master Handover
148(1)
4.8 Serial Buses
149(20)
5 Memory Circuits and Systems
169(106)
5.1 Static Random Access Memory
170(9)
5.2 Synchronous Dynamic Random Access Memory
179(22)
5.3 Electrically-Erasable-Programmable-Read-Only-Memory
201(8)
5.4 Flash Memory
209(44)
5.5 Serial Rash Memory
253(22)
References
274(1)
6 Central Processing Unit
275(102)
6.1 RISC Instruction Formats
275(2)
6.2 CPU Data-Path
277(3)
6.3 Fixed-Point Register-to-Register Type ALU Instructions
280(12)
6.4 Fixed-Point Immediate Type ALU Instructions
292(6)
6.5 Data Movement Instructions
298(4)
6.6 Program Control Instructions
302(6)
6.7 Design Example I: A Fixed-Point CPU with Four Instructions
308(5)
6.8 Design Example II: A Fixed-Point CPU with Eight Instructions
313(3)
6.9 Floating-Point Instructions
316(1)
6.10 Floating-Point
317(5)
6.11 Floating-Point Adder
322(2)
6.12 Floating-Point Multiplier
324(1)
6.13 A RISC CPU with Fixed and Floating-Point Units
325(2)
6.14 Structural Hazards
327(1)
6.15 Data Hazards
328(5)
6.16 Program Control Hazards
333(2)
6.17 Handling Hazards in a Five-Stage RISC CPU: An Example
335(4)
6.18 Handling Hazards in a Four-Stage RISC CPU
339(1)
6.19 Handling Hazards in a Three-Stage RISC CPU
340(2)
6.20 Multi-cycle ALU and Related Data Hazards
342(4)
6.21 Cache Topologies
346(3)
6.22 Cache Write and Read Structures
349(2)
6.23 A Direct-Mapped Cache Example
351(3)
6.24 Write-Through and Write-Back Cache Structures in Set-Associative Caches
354(1)
6.25 A Two-Way Set-Associative Write-Through Cache Example
355(3)
6.26 A Two-Way Set-Associative Write-Back Cache Example
358(19)
References
375(2)
7 System Peripherals
377(78)
7.1 Overall System Arcitecture
377(1)
7.2 Direct Memory Access Controller
378(9)
7.3 Interrupt Controller
387(12)
7.4 Serial Transmitter and Receiver Interface
399(7)
7.5 Timers
406(8)
7.6 Display Adaptor
414(11)
7.7 Data Converters
425(12)
7.8 Digital-to-Analog Converter (DAC)
437(18)
References
454(1)
8 Special Topics
455(36)
8.1 Field-Programmable-Gate Array
455(18)
8.2 Data-Driven Processors
473(18)
References
489(2)
Appendix: An Introduction to Verilog Hardware Design Language 491(38)
Index 529
Ahmet Bindal received his M.S. and Ph.D. degrees in Electrical Engineering Department from the University of California, Los Angeles CA. His doctoral research was the material characterization for high electron mobility GaAs transistors. During his graduate program, he was a graduate research associate and technical consultant for Hughes Aircraft Co. In 1988, he joined the technical staff of IBM Research and Development Center in Fishkill, NY, where he worked as a device design and characterization engineer. He developed asymmetrical MOS transistors and ultra thin Silicon-On-Insulator (SOI) technologies for IBM. In 1993, he transferred to IBM in Rochester, MN, as a senior circuit design engineer to work on the floating-point unit for AS-400 main frame processor. He continued his circuit design career at Intel Corporation in Santa Clara, CA, where he designed 16-bit packed multipliers and adders for the MMX unit for Pentium II processors. In 1996, he joined Philips Semiconductors in Sunnyvale, CA, where he was involved in the designs of instruction/data caches and various SRAM modules for the Trimedia processor. His involvement with VLSI architecture started in Philips Semiconductors and led to the design of the Video-Out and Image Co-Processor units for the same processor. In 1998, he joined Cadence Design Systems as a VLSI architect and directed a team of engineers to design self-timed asynchronous processors. Staring 2000 he implemented 802.11a and 802.11b wireless LAN protocols in VLSI. After approximately 20 years of industry work, he joined the Computer Engineering faculty at San Jose State University in 2002. His current research interests range from Nano-Scale Electron Devices to VLSI Design and Nano-Scale Architectures. Dr. Bindal has over 20 scientific journal and conference publications and 10 invention disclosures with IBM; he currently holds 3 U.S. patents with IBM and 1 with Intel Corporation.