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Fundamentals of Digital Logic with Verilog Design 3rd edition [Kõva köide]

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  • Formaat: Hardback, 864 pages, kõrgus x laius x paksus: 234x193x38 mm, kaal: 1413 g, 910 Illustrations
  • Ilmumisaeg: 16-Mar-2013
  • Kirjastus: McGraw Hill Higher Education
  • ISBN-10: 0073380547
  • ISBN-13: 9780073380544
Teised raamatud teemal:
Fundamentals of Digital Logic with Verilog Design 3rd editionSuurem pilt
  • Formaat: Hardback, 864 pages, kõrgus x laius x paksus: 234x193x38 mm, kaal: 1413 g, 910 Illustrations
  • Ilmumisaeg: 16-Mar-2013
  • Kirjastus: McGraw Hill Higher Education
  • ISBN-10: 0073380547
  • ISBN-13: 9780073380544
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780073380544.html
Märksõnad:
Teaches the basic design techniques for logic circuits. This book emphasizes the synthesis of circuits and explains how circuits are implemented in real chips. It supports various major features of the commercial product and comes with a compiler for the IEEE standard Verilog language.

Fundamentals of Digital Logic With Verilog Designteaches the basic design techniques for logic circuits. It emphasizes the synthesis of circuits and explains how circuits are implemented in real chips. Fundamental concepts are illustrated by using small examples.

Use of CAD software is well integrated into the book. A CD-ROM that contains Altera's Quartus CAD software comes free with every copy of the text. The CAD software provides automatic mapping of a design written in Verilog into Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Students will be able to try, firsthand, the book's Verilog examples (over 140) and homework problems.

Engineers use Quartus CAD for designing, simulating, testing and implementing logic circuits. The version included with this text supports all major features of the commercial product and comes with a compiler for the IEEE standard Verilog language. Students will be able to:

enter a design into the CAD system

compile the design into a selected device

simulate the functionality and timing of the resulting circuit

implement the designs in actual devices (using the school's laboratory facilities)

Verilog is a complex language, so it is introduced gradually in the book. Each Verilog feature is presented as it becomes pertinent for the circuits being discussed. To teach the student to use the Quartus CAD, the book includes three tutorials.

Chapter 1 Introduction
1(20)
1.1 Digital Hardware
2(4)
1.1.1 Standard Chips
4(1)
1.1.2 Programmable Logic Devices
5(1)
1.1.3 Custom-Designed Chips
5(1)
1.2 The Design Process
6(2)
1.3 Structure of a Computer
8(1)
1.4 Logic Circuit Design in This Book
8(3)
1.5 Digital Representation of Information
11(5)
1.5.1 Binary Numbers
12(1)
1.5.2 Conversion between Decimal and Binary Systems
13(1)
1.5.3 ASCII Character Code
14(2)
1.5.4 Digital and Analog Information
16(1)
1.6 Theory and Practice
16(5)
Problems
18(1)
References
19(2)
Chapter 2 Introduction to Logic Circuits
21(100)
2.1 Variables and Functions
22(3)
2.2 Inversion
25(1)
2.3 Truth Tables
26(1)
2.4 Logic Gates and Networks
27(6)
2.4.1 Analysis of a Logic Network
29(4)
2.5 Boolean Algebra
33(10)
2.5.1 The Venn Diagram
37(5)
2.5.2 Notation and Terminology
42(1)
2.5.3 Precedence of Operations
43(1)
2.6 Synthesis Using AND, OR, and NOT Gates
43(11)
2.6.1 Sum-of-Products and Product-of-Sums Forms
48(6)
2.7 NAND and NOR Logic Networks
54(5)
2.8 Design Examples
59(5)
2.8.1 Three-Way Light Control
59(1)
2.8.2 Multiplexer Circuit
60(3)
2.8.3 Number Display
63(1)
2.9 Introduction to CAD Tools
64(4)
2.9.1 Design Entry
64(2)
2.9.2 Logic Synthesis
66(1)
2.9.3 Functional Simulation
67(1)
2.9.4 Physical Design
67(1)
2.9.5 Timing Simulation
67(1)
2.9.6 Circuit Implementation
68(1)
2.9.7 Complete Design Flow
68(1)
2.10 Introduction to Verilog
68(10)
2.10.1 Structural Specification of Logic Circuits
70(2)
2.10.2 Behavioral Specification of Logic Circuits
72(4)
2.10.3 Hierarchical Verilog Code
76(2)
2.10.4 How NOT to Write Verilog Code
78(1)
2.11 Minimization and Karnaugh Maps
78(9)
2.12 Strategy for Minimization
87(4)
2.12.1 Terminology
87(2)
2.12.2 Minimization Procedure
89(2)
2.13 Minimization of Product-of-Sums Forms
91(3)
2.14 Incompletely Specified Functions
94(2)
2.15 Multiple-Output Circuits
96(5)
2.16 Concluding Remarks
101(1)
2.17 Examples of Solved Problems
101(20)
Problems
111(9)
References
120(1)
Chapter 3 Number Representation and Arithmetic Circuits
121(68)
3.1 Positional Number Representation
122(3)
3.1.1 Unsigned Integers
122(1)
3.1.2 Octal and Hexadecimal Representations
123(2)
3.2 Addition of Unsigned Numbers
125(7)
3.2.1 Decomposed Full-Adder
129(1)
3.2.2 Ripple-Carry Adder
129(1)
3.2.3 Design Example
130(2)
3.3 Signed Numbers
132(13)
3.3.1 Negative Numbers
133(2)
3.3.2 Addition and Subtraction
135(3)
3.3.3 Adder and Subtractor Unit
138(1)
3.3.4 Radix-Complement Schemes*
139(4)
3.3.5 Arithmetic Overflow
143(2)
3.3.6 Performance Issues
145(1)
3.4 Fast Adders
145(6)
3.4.1 Carry-Lookahead Adder
146(5)
3.5 Design of Arithmetic Circuits Using CAD Tools
151(16)
3.5.1 Design of Arithmetic Circuits Using Schematic Capture
151(1)
3.5.2 Design of Arithmetic Circuits Using Verilog
152(3)
3.5.3 Using Vectored Signals
155(1)
3.5.4 Using a Generic Specification
156(2)
3.5.5 Nets and Variables in Verilog
158(1)
3.5.6 Arithmetic Assignment Statements
159(4)
3.5.7 Module Hierarchy in Verilog Code
163(3)
3.5.8 Representation of Numbers in Verilog Code
166(1)
3.6 Multiplication
167(3)
3.6.1 Array Multiplier for Unsigned Numbers
167(2)
3.6.2 Multiplication of Signed Numbers
169(1)
3.7 Other Number Representations
170(8)
3.7.1 Fixed-Point Numbers
170(2)
3.7.2 Floating-Point Numbers
172(2)
3.7.3 Binary-Coded-Decimal Representation
174(4)
3.8 Examples of Solved Problems
178(11)
Problems
184(4)
References
188(1)
Chapter 4 Combinational-Clrcuit Building Blocks
189(58)
4.1 Multiplexers
190(11)
4.1.1 Synthesis of Logic Functions Using Multiplexers
193(3)
4.1.2 Multiplexer Synthesis Using Shannon's Expansion
196(5)
4.2 Decoders
201(4)
4.2.1 Demultiplexers
203(2)
4.3 Encoders
205(3)
4.3.1 Binary Encoders
205(1)
4.3.2 Priority Encoders
205(3)
4.4 Code Converters
208(1)
4.5 Arithmetic Comparison Circuits
208(2)
4.6 Verilog for Combinational Circuits
210(22)
4.6.1 The Conditional Operator
210(2)
4.6.2 The If-Else Statement
212(3)
4.6.3 The Case Statement
215(6)
4.6.4 The For Loop
221(2)
4.6.5 Verilog Operators
223(5)
4.6.6 The Generate Construct
228(1)
4.6.7 Tasks and Functions
229(3)
4.7 Concluding Remarks
232(1)
4.8 Examples of Solved Problems
233(14)
Problems
243(3)
References
246(1)
Chapter 5 Flip-Flops, Registers, and Counters
247(84)
5.1 Basic Latch
249(2)
5.2 Gated SR Latch
251(2)
5.2.1 Gated SR Latch with NAND Gates
253(1)
5.3 Gated D Latch
253(3)
5.3.1 Effects of Propagation Delays
255(1)
5.4 Edge-Triggered D Flip-Flops
256(7)
5.4.1 Master-Slave D Flip-Flop
256(2)
5.4.2 Other Types of Edge-Triggered D Flip-Flops
258(2)
5.4.3 D Flip-Flops with Clear and Preset
260(3)
5.4.4 Flip-Flop Timing Parameters
263(1)
5.5 T Flip-Flop
263(1)
5.6 JK Flip-Flop
264(2)
5.7 Summary of Terminology
266(1)
5.8 Registers
267(2)
5.8.1 Shift Register
267(1)
5.8.2 Parallel-Access Shift Register
267(2)
5.9 Counters
269(9)
5.9.1 Asynchronous Counters
269(3)
5.9.2 Synchronous Counters
272(4)
5.9.3 Counters with Parallel Load
276(2)
5.10 Reset Synchronization
278(2)
5.11 Other Types of Counters
280(4)
5.11.1 BCD Counter
280(1)
5.11.2 Ring Counter
280(3)
5.11.3 Johnson Counter
283(1)
5.11.4 Remarks on Counter Design
283(1)
5.12 Using Storage Elements with CAD Tools
284(11)
5.12.1 Including Storage Elements in Schematics
284(1)
5.12.2 Using Verilog Constructs for Storage Elements
285(3)
5.12.3 Blocking and Non-Blocking Assignments
288(5)
5.12.4 Non-Blocking Assignments for Combinational Circuits
293(1)
5.12.5 Flip-Flops with Clear Capability
293(2)
5.13 Using Verilog Constructs for Registers and Counters
295(7)
5.13.1 Flip-Flops and Registers with Enable Inputs
300(2)
5.13.2 Shift Registers with Enable Inputs
302(1)
5.14 Design Example
302(8)
5.14.1 Reaction Timer
302(7)
5.14.2 Register Transfer Level (RTL) Code
309(1)
5.15 Timing Analysis of Flip-flop Circuits
310(4)
5.15.1 Timing Analysis with Clock Skew
312(2)
5.16 Concluding Remarks
314(1)
5.17 Examples of Solved Problems
315(16)
Problems
321(8)
References
329(2)
Chapter 6 Synchronous Sequential Circuits
331(90)
6.1 Basic Design Steps
333(11)
6.1.1 State Diagram
333(2)
6.1.2 State Table
335(1)
6.1.3 State Assignment
336(1)
6.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions
337(2)
6.1.5 Timing Diagram
339(1)
6.1.6 Summary of Design Steps
340(4)
6.2 State-Assignment Problem
344(5)
6.2.1 One-Hot Encoding
347(2)
6.3 Mealy State Model
349(5)
6.4 Design of Finite State Machines Using CAD Tools
354(9)
6.4.1 Verilog Code for Moore-Type FSMs
355(1)
6.4.2 Synthesis of Verilog Code
356(2)
6.4.3 Simulating and Testing the Circuit
358(1)
6.4.4 Alternative Styles of Verilog Code
359(1)
6.4.5 Summary of Design Steps When Using CAD Tools
360(1)
6.4.6 Specifying the State Assignment in Verilog Code
361(2)
6.4.7 Specification of Mealy FSMs Using Verilog
363(1)
6.5 Serial Adder Example
363(9)
6.5.1 Mealy-Type FSM for Serial Adder
364(3)
6.5.2 Moore-Type FSM for Serial Adder
367(3)
6.5.3 Verilog Code for the Serial Adder
370(2)
6.6 State Minimization
372(11)
6.6.1 Partitioning Minimization Procedure
374(7)
6.6.2 Incompletely Specified FSMs
381(2)
6.7 Design of a Counter Using the Sequential Circuit Approach
383(10)
6.7.1 State Diagram and State Table for a Modulo-8 Counter
383(1)
6.7.2 State Assignment
384(1)
6.7.3 Implementation Using D-Type Flip-Flops
385(1)
6.7.4 Implementation Using JK-Type Flip-Flops
386(4)
6.7.5 Example---A Different Counter
390(3)
6.8 FSM as an Arbiter Circuit
393(4)
6.9 Analysis of Synchronous Sequential Circuits
397(4)
6.10 Algorithmic State Machine (ASM) Charts
401(4)
6.11 Formal Model for Sequential Circuits
405(2)
6.12 Concluding Remarks
407(1)
6.13 Examples of Solved Problems
407(14)
Problems
416(4)
References
420(1)
Chapter 7 Digital System Design
421(70)
7.1 Bus Structure
422(7)
7.1.1 Using Tri-State Drivers to Implement a Bus
422(2)
7.1.2 Using Multiplexers to Implement a Bus
424(2)
7.1.3 Verilog Code for Specification of Bus Structures
426(3)
7.2 Simple Processor
429(12)
7.3 A Bit-Counting Circuit
441(5)
7.4 Shift-and-Add Multiplier
446(9)
7.5 Divider
455(11)
7.6 Arithmetic Mean
466(4)
7.7 Sort Operation
470(8)
7.8 Clock Synchronization and Timing Issues
478(7)
7.8.1 Clock Distribution
478(3)
7.8.2 Flip-Flop Timing Parameters
481(1)
7.8.3 Asynchronous Inputs to Flip-Flops
482(1)
7.8.4 Switch Debouncing
483(2)
7.9 Concluding Remarks
485(6)
Problems
485(4)
References
489(2)
Chapter 8 Optimized Implementation of Logic Functions
491(60)
8.1 Multilevel Synthesis
492(12)
8.1.1 Factoring
493(3)
8.1.2 Functional Decomposition
496(6)
8.1.3 Multilevel NAND and NOR Circuits
502(2)
8.2 Analysis of Multilevel Circuits
504(6)
8.3 Alternative Representations of Logic Functions
510(10)
8.3.1 Cubical Representation
510(4)
8.3.2 Binary Decision Diagrams
514(6)
8.4 Optimization Techniques Based on Cubical Representation
520(17)
8.4.1 A Tabular Method for Minimization
521(8)
8.4.2 A Cubical Technique for Minimization
529(7)
8.4.3 Practical Considerations
536(1)
8.5 Concluding Remarks
537(1)
8.6 Examples of Solved Problems
537(14)
Problems
546(3)
References
549(2)
Chapter 9 Asynchronous Sequential Circuits
551(86)
9.1 Asynchronous Behavior
552(4)
9.2 Analysis of Asynchronous Circuits
556(8)
9.3 Synthesis of Asynchronous Circuits
564(13)
9.4 State Reduction
577(15)
9.5 State Assignment
592(16)
9.5.1 Transition Diagram
595(3)
9.5.2 Exploiting Unspecified Next-State Entries
598(4)
9.5.3 State Assignment Using Additional State Variables
602(5)
9.5.4 One-Hot State Assignment
607(1)
9.6 Hazards
608(8)
9.6.1 Static Hazards
609(4)
9.6.2 Dynamic Hazards
613(1)
9.6.3 Significance of Hazards
614(2)
9.7 A Complete Design Example
616(5)
9.7.1 The Vending-Machine Controller
616(5)
9.8 Concluding Remarks
621(2)
9.9 Examples of Solved Problems
623(14)
Problems
631(4)
References
635(2)
Chapter 10 Computer Aided Design Tools
637(16)
10.1 Synthesis
638(6)
10.1.1 Netlist Generation
638(1)
10.1.2 Gate Optimization
638(2)
10.1.3 Technology Mapping
640(4)
10.2 Physical Design
644(6)
10.2.1 Placement
646(1)
10.2.2 Routing
647(1)
10.2.3 Static Timing Analysis
648(2)
10.3 Concluding Remarks
650(3)
References
651(2)
Chapter 11 Testing of Logic Circuits
653(32)
11.1 Fault Model
654(1)
11.1.1 Stuck-at Model
654(1)
11.1.2 Single and Multiple Faults
655(1)
11.1.3 CMOS Circuits
655(1)
11.2 Complexity of a Test Set
655(2)
11.3 Path Sensitizing
657(4)
11.3.1 Detection of a Specific Fault
659(2)
11.4 Circuits with Tree Structure
661(1)
11.5 Random Tests
662(3)
11.6 Testing of Sequential Circuits
665(4)
11.6.1 Design for Testability
665(4)
11.7 Built-in Self-Test
669(7)
11.7.1 Built-in Logic Block Observer
673(2)
11.7.2 Signature Analysis
675(1)
11.7.3 Boundary Scan
676(1)
11.8 Printed Circuit Boards
676(4)
11.8.1 Testing of PCBs
678(1)
11.8.2 Instrumentation
679(1)
11.9 Concluding Remarks
680(5)
Problems
680(3)
References
683(2)
Appendix A Verilog Reference
685(48)
A.1 Documentation in Verilog Code
686(1)
A.2 White Space
686(1)
A.3 Signals in Verilog Code
686(1)
A.4 Identifier Names
687(1)
A.5 Signal Values, Numbers, and Parameters
687(1)
A.5.1 Parameters
688(1)
A.6 Net and Variable Types
688(2)
A.6.1 Nets
688(1)
A.6.2 Variables
689(1)
A.6.3 Memories
690(1)
A.7 Operators
690(2)
A.8 Verilog Module
692(2)
A.9 Gate Instantiations
694(2)
A.10 Concurrent Statements
696(2)
A.10.1 Continuous Assignments
696(1)
A.10.2 Using Parameters
697(1)
A.11 Procedural Statements
698(11)
A.11.1 Always and Initial Blocks
698(2)
A.11.2 The If-Else Statement
700(1)
A.11.3 Statement Ordering
701(1)
A.11.4 The Case Statement
702(1)
A.11.5 Casez and Casex Statements
703(1)
A.11.6 Loop Statements
704(4)
A.11.7 Blocking versus Non-blocking Assignments for Combinational Circuits
708(1)
A.12 Using Subcircuits
709(4)
A.12.1 Subcircuit Parameters
710(2)
A.12.2 The Generate Capability
712(1)
A.13 Functions and Tasks
713(3)
A.14 Sequential Circuits
716(9)
A.14.1 A Gated D Latch
717(1)
A.14.2 D Flip-Flop
717(1)
A.14.3 Flip-Flops with Reset
718(1)
A.14.4 Registers
718(2)
A.14.5 Shift Registers
720(1)
A.14.6 Counters
721(1)
A.14.7 An Example of a Sequential Circuit
722(1)
A.14.8 Moore-Type Finite State Machines
723(1)
A.14.9 Mealy-Type Finite State Machines
724(1)
A.15 Guidelines for Writing Verilog Code
725(6)
A.16 Concluding Remarks
731(2)
References
731(2)
Appendix B Implementation Technology
733(92)
B.1 Transistor Switches
734(2)
B.2 NMOS Logic Gates
736(3)
B.3 CMOS Logic Gates
739(8)
B.3.1 Speed of Logic Gate Circuits
746(1)
B.4 Negative Logic System
747(2)
B.5 Standard Chips
749(4)
B.5.1 7400-Series Standard Chips
749(4)
B.6 Programmable Logic Devices
753(16)
B.6.1 Programmable Logic Array (PLA)
754(3)
B.6.2 Programmable Array Logic (PAL)
757(2)
B.6.3 Programming of PLAs and PALs
759(2)
B.6.4 Complex Programmable Logic Devices (CPLDs)
761(3)
B.6.5 Field-Programmable Gate Arrays
764(5)
B.7 Custom Chips, Standard Cells, and Gate Arrays
769(2)
B.8 Practical Aspects
771(23)
B.8.1 MOSFET Fabrication and Behavior
771(4)
B.8.2 MOSFET On-Resistance
775(1)
B.8.3 Voltage Levels in Logic Gates
776(2)
B.8.4 Noise Margin
778(1)
B.8.5 Dynamic Operation of Logic Gates
779(3)
B.8.6 Power Dissipation in Logic Gates
782(2)
B.8.7 Passing 1s and 0s Through Transistor Switches
784(2)
B.8.8 Transmission Gates
786(2)
B.8.9 Fan-in and Fan-out in Logic Gates
788(4)
B.8.10 Tri-state Drivers
792(2)
B.9 Static Random Access Memory (SRAM)
794(3)
B.9.1 SRAM Blocks in PLDs
797(1)
B.10 Implementation Details for SPLDs, CPLDs, and FPGAs
797(9)
B.10.1 Implementation in FPGAs
804(2)
B.11 Concluding Remarks
806(1)
B.12 Examples of Solved Problems
807(18)
Problems
814(9)
References
823(2)
Answers 825(14)
Index 839
Stephen Brown received the Ph.D. and M.A.Sc. degrees in Electrical Engineering from the University of Toronto, and his B.A.Sc. degree in Electrical Engineering from the University of New Brunswick. He joined the University of Toronto faculty in 1992, where he is now a Professor in the Department of Electrical & Computer Engineering. He is also the Director of FPGA Academic Programs for Intel Corporation. His research interests include field-programmable VLSI technology, CAD algorithms, computer architecture, and applications of machine learning. He won the Canadian Natural Sciences and Engineering Research Councils 1992 Doctoral Prize for the best Ph.D. thesis in Canada, and the New Brunswick Governor-Generals 1985 award for the highest academic standing in the Faculty of Engineering. He is a coauthor of more than 150 scientific research papers and two other textbooks: Fundamentals of Digital Logic with Verilog Design and Field-Programmable Gate Arrays. He has won many awards for excellence in teaching electrical engineering, computer engineering, and computer science courses.





Zvonko Vranesic received his B.A.Sc., M.A.Sc., and Ph.D. degrees, all in Electrical Engineering, from the University of Toronto. From 1963 to 1965 he worked as a design engineer with the Northern Electric Co. Ltd. in Bramalea, Ontario. In 1968 he joined the University of Toronto, where he is now a Professor Emeritus in the Department of Electrical & Computer Engineering. During the 197879 academic year, he was a Senior Visitor at the University of Cambridge, England, and during 198485 he was at the University of Paris, 6. From 1995 to 2000 he served as Chair of the Division of Engineering Science at the University of Toronto. He is a coauthor of four other books: Computer Organization and Embedded Systems, 6th ed.; Fundamentals of Digital Logic with Verilog Design, 3rd ed.; Microcomputer Structures; and Field-Programmable Gate Arrays. In 1990, he received the Wighton Fellowship for innovative and distinctive contributions to undergraduate laboratory instruction. In 2004, he received the Faculty Teaching Award from the Faculty of Applied Science and Engineering at the University of Toronto. He has represented Canada in numerous chess competitions. He holds the title of International Master.