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Fundamentals of Modern VLSI Devices 3rd Revised edition [Kõva köide]

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  • Formaat: Hardback, 622 pages, kõrgus x laius x paksus: 250x173x32 mm, kaal: 1330 g, Worked examples or Exercises
  • Ilmumisaeg: 02-Dec-2021
  • Kirjastus: Cambridge University Press
  • ISBN-10: 1108480020
  • ISBN-13: 9781108480024
Teised raamatud teemal:
Fundamentals of Modern VLSI Devices 3rd Revised editionSuurem pilt
  • Formaat: Hardback, 622 pages, kõrgus x laius x paksus: 250x173x32 mm, kaal: 1330 g, Worked examples or Exercises
  • Ilmumisaeg: 02-Dec-2021
  • Kirjastus: Cambridge University Press
  • ISBN-10: 1108480020
  • ISBN-13: 9781108480024
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781108480024.html
Märksõnad:
A thoroughly updated third edition of an classic text, perfect for practical transistor design and in the classroom. It includes a variety of recent developments, reorganized chapters, and additional end-of-chapter homework exercises, making it ideal for senior undergraduate and graduate students taking advanced semiconductor devices courses.

A thoroughly updated third edition of an classic and widely adopted text, perfect for practical transistor design and in the classroom. Covering a variety of recent developments, the internationally renowned authors discuss in detail the basic properties and designs of modern VLSI devices, as well as factors affecting performance. Containing around 25% new material, coverage has been expanded to include high-k gate dielectrics, metal gate technology, strained silicon mobility, non-GCA (Gradual Channel Approximation) modelling of MOSFETs, short-channel FinFETS, and symmetric lateral bipolar transistors on SOI. Chapters have been reorganized to integrate the appendices into the main text to enable a smoother learning experience, and numerous additional end-of-chapter homework exercises (+30%) are included to engage students with real-world problems and test their understanding. A perfect text for senior undergraduate and graduate students taking advanced semiconductor devices courses, and for practicing silicon device professionals in the semiconductor industry.

Muu info

A thoroughly updated third edition of this classic text, perfect for practical transistor design and in the classroom.
Preface to the Third Edition xiii
Preface to the Second Edition xv
Preface to the First Edition xvii
Physical Constants and Unit Conversions xix
List of Symbols xx
1 Introduction 1(8)
1.1 Evolution of VLSI Device Technology
1(4)
1.1.1 Historical Perspective
1(2)
1.1.2 Recent Developments
3(2)
1.2 Scope and Brief Description of the Book
5(4)
2 Basic Device Physics 9(34)
2.1 Energy Bands in Silicon
9(6)
2.1.1 Bandgap of Silicon
9(1)
2.1.2 Density of States
10(2)
2.1.3 Distribution Function: Fermi Level
12(1)
2.1.4 Carrier Concentration
13(2)
2.2 n-Type and p-Type Silicon
15(6)
2.2.1 Donors and Acceptors
15(2)
2.2.2 Fermi Level in Extrinsic Silicon
17(3)
2.2.3 Degenerately Doped Silicon
20(1)
2.3 Carrier Transport in Silicon
21(7)
2.3.1 Drift Current: Mobility
22(3)
2.3.2 Velocity Saturation
25(1)
2.3.3 Diffusion Current
25(2)
2.3.4 Einstein Relations
27(1)
2.4 Basic Equations for Device Operation
28(12)
2.4.1 Poisson's Equation: Electrostatic Potential
28(4)
2.4.2 Current-Density Equations
32(3)
2.4.3 Generation and Recombination
35(3)
2.4.4 Current Continuity Equations
38(2)
Exercises
40(3)
3 p-n Junctions and Metal-Silicon Contacts 43(56)
3.1 p-n Junctions
43(31)
3.1.1 Energy-Band Diagrams and Built-in Potential for a p-n Diode
44(1)
3.1.2 Depletion Approximation
45(8)
3.1.3 Spatial Variation of Quasi-Fermi Potentials
53(9)
3.1.4 The Diode Equation
62(3)
3.1.5 Current-Voltage Characteristics Governed by the Diode Equation
65(2)
3.1.6 Space-Charge-Region Current
67(3)
3.1.7 Measured Diode Current and Ideality Factor
70(1)
3.1.8 Temperature Dependence and Magnitude of Diode Leakage Currents
71(1)
3.1.9 Minority-Carrier Mobility, Lifetime, and Diffusion Length
72(2)
3.2 Metal-Silicon Contacts
74(15)
3.2.1 Static Characteristics of a Schottky Diode
74(8)
3.2.2 Current-Voltage Characteristics of a Schottky Diode
82(5)
3.2.3 Ohmic Contacts
87(2)
3.3 High-Field Effects in Reverse-Biased Diodes
89(5)
3.3.1 Impact Ionization and Avalanche Breakdown
90(3)
3.3.2 Band-to-Band Tunneling
93(1)
Exercises
94(5)
4 MOS Capacitors 99(72)
4.1 Energy Band Diagram of an MOS System
99(7)
4.1.1 Free Electron Level, Work Function, and Flatband Voltage
99(3)
4.1.2 Gate Voltage, Surface Potential, and Charge in Silicon
102(1)
4.1.3 Accumulation, Depletion, and Inversion
103(3)
4.2 Electrostatic Potential and Charge Distribution in Silicon
106(8)
4.2.1 Solving Poisson's Equation
106(6)
4.2.2 Surface Potential and Charge Density as a Function of Gate Voltage
112(2)
4.3 Capacitance-Voltage Characteristics of MOS Capacitors
114(15)
4.3.1 Measurement Setup
114(1)
4.3.2 Capacitance Components in MOS
114(1)
4.3.3 C-V Characteristics in Different Bias Regions
115(4)
4.3.4 Split C-V Measurement
119(2)
4.3.5 Polysilicon Gate: Work Function and Depletion Effects
121(4)
4.3.6 MOS under Nonequilibrium
125(4)
4.4 Quantum Mechanical Effects in MOS
129(7)
4.4.1 Coupled Poisson-Schrodinger's Equations
129(1)
4.4.2 Quantum Effect on Inversion-Layer Depth
129(2)
4.4.3 Quantum-Mechanical Solution in Weak Inversion
131(5)
4.5 Interface States and Charge Traps in Oxide
136(13)
4.5.1 Effect of Oxide Charge on Flatband Voltage
137(1)
4.5.2 Interface-State Capacitance and Conductance
138(9)
4.5.3 Distributed Circuit Model for Oxide Traps
147(2)
4.6 High-Field Effects in Oxide and Oxide Degradation
149(18)
4.6.1 Tunneling into and through Silicon Dioxide
149(9)
4.6.2 Injection of Hot Carriers from Silicon into Silicon Dioxide
158(2)
4.6.3 High-Field Effects in Gated Diodes
160(2)
4.6.4 Dielectric Breakdown
162(5)
Exercises
167(4)
5 MOSFETs: Long Channel 171(35)
5.1 MOSFET I-V Characteristics
172(20)
5.1.1 Gradual Channel Approximation
173(3)
5.1.2 Charge Sheet Model
176(2)
5.1.3 Regional I-V Models
178(9)
5.1.4 Non-GCA Model for the Saturation Region
187(5)
5.1.5 pMOSFET I-V Characteristics
192(1)
5.2 MOSFET Channel Mobility
192(6)
5.2.1 Empirical Universal Mobility
192(4)
5.2.2 Strain Effect on Mobility
196(2)
5.3 MOSFET Threshold Voltage
198(4)
5.3.1 Substrate Sensitivity (Body Effect)
198(1)
5.3.2 Temperature Dependence of Threshold Voltage
199(2)
5.3.3 Quantum Effect on Threshold Voltage
201(1)
5.4 MOSFET Capacitance
202(1)
Exercises
203(3)
6 MOSFETs: Short Channel 206(58)
6.1 Short-Channel Effect
206(13)
6.1.1 Threshold Voltage Roll-off
206(4)
6.1.2 Analytic Solutions to 2-D Poisson's Equation in Subthreshold
210(9)
6.2 High-Field Transport
219(17)
6.2.1 Velocity Saturation
219(10)
6.2.2 Nonlocal Transport
229(7)
6.3 MOSFET Threshold Voltage and Channel Profile Design
236(20)
6.3.1 Threshold Voltage Requirement
237(4)
6.3.2 Channel Profile Design
241(5)
6.3.3 Nonuniform Channel Doping
246(7)
6.3.4 Discrete Dopant Effects on Threshold Voltage
253(3)
6.4 MOSFET Degradation and Breakdown at High Fields
256(6)
6.4.1 Hot-Carrier Effects
257(2)
6.4.2 Negative-Bias-Temperature Instability
259(1)
6.4.3 MOSFET Breakdown
260(2)
Exercises
262(2)
7 Silicon-on-Insulator and Double-Gate MOSFETs 264(31)
7.1 SOI MOSFETs
265(11)
7.1.1 Long-Channel SOI MOSFETs
265(6)
7.1.2 Short-Channel SOI MOSFETs
271(5)
7.2 Double-Gate and Nanowire MOSFETs
276(16)
7.2.1 Analytic Potential Model for Symmetric DG MOSFETs
277(4)
7.2.2 Short-Channel DG MOSFETs
281(6)
7.2.3 Nanowire MOSFETs
287(4)
7.2.4 Scaling Limits of DG and Nanowire MOSFETs
291(1)
Exercises
292(3)
8 CMOS Performance Factors 295(66)
8.1 MOSFET Scaling
295(3)
8.1.1 Constant-Field Scaling
295(2)
8.1.2 Nonscaling Factors
297(1)
8.2 Basic CMOS Circuit Elements
298(18)
8.2.1 CMOS Inverters
299(10)
8.2.2 CMOS NAND and NOR Gates
309(4)
8.2.3 Inverter and NAND Layouts
313(3)
8.3 Parasitic Elements
316(16)
8.3.1 Source-Drain Resistance
317(4)
8.3.2 Parasitic Capacitances
321(3)
8.3.3 Gate Resistance
324(2)
8.3.4 Interconnect R and C
326(6)
8.4 Sensitivity of CMOS Delay to Device Parameters
332(20)
8.4.1 Propagation Delay and Delay Equation
333(6)
8.4.2 Delay Sensitivity to Channel Width, Length, and Gate Oxide Thickness
339(4)
8.4.3 Sensitivity of Delay to Power-Supply Voltage and Threshold Voltage
343(1)
8.4.4 Sensitivity of Delay to Parasitic Resistance and Capacitance
344(4)
8.4.5 Effect of Transport Parameters on CMOS Delay
348(1)
8.4.6 Delay of Two-Way NAND Gates
349(3)
8.5 Performance Factors of MOSFETs in RF Circuits
352(6)
8.5.1 Small-Signal Equivalent Circuit
353(1)
8.5.2 Unity-Current-Gain Frequency
354(1)
8.5.3 Power Gain Condition of a Two-Port Network
354(1)
8.5.4 Unity Power-Gain Frequency
355(3)
Exercises
358(3)
9 Bipolar Devices 361(64)
9.1 Basic Operation of a Bipolar Transistor
365(5)
9.1.1 Modifying the Simple Diode Theory for Describing Bipolar Transistors
365(5)
9.2 Ideal Current-Voltage Characteristics
370(15)
9.2.1 Intrinsic-Base Resistance and Emitter Current Crowding
371(4)
9.2.2 Collector Current
375(3)
9.2.3 Base Current
378(4)
9.2.4 Current Gains
382(2)
9.2.5 Ideal IC-VCE Characteristics
384(1)
9.3 Measured Characteristics of Typical n-p-n Transistors
385(15)
9.3.1 Effect of Emitter and Base Series Resistances
386(3)
9.3.2 Effect of Base-Collector Voltage on Collector Current
389(3)
9.3.3 Collector-Current Falloff
392(4)
9.3.4 Excess Base Current Associated with Extrinsic-Base-Emitter Junction
396(4)
9.4 Base Transit Time
400(1)
9.5 Diffusion Capacitance in an Emitter-Base Diode
401(6)
9.5.1 Small-Signal Current in a Forward-Biased Diode
401(4)
9.5.2 Low-Frequency [ ωτpE < 1 and ωtB < 1] Diffusion Capacitance
405(1)
9.5.3 Diffusion Capacitance at High Frequencies [ ωτpE > 1]
406(1)
9.6 Bipolar Device Models for Circuit Analyses
407(9)
9.6.1 Basic Steady-State Model
407(2)
9.6.2 Basic ac Model
409(7)
9.7 Breakdown Voltages
416(5)
9.7.1 Common-Base Current Gain in the Presence of Base-Collector Junction Avalanche
417(1)
9.7.2 Saturation Currents in a Transistor
418(1)
9.7.3 Relation between BVCEO and BVCBO
419(2)
9.7.4 Breakdown Voltages of Symmetric Lateral Bipolar Transistors on SOI
421(1)
Exercises
421(4)
10 Bipolar Device Design 425(60)
10.1 Design of the Emitter of a Vertical Bipolar Transistor
425(2)
10.1.1 Diffused or Implanted-and-Diffused Emitter
426(1)
10.1.2 Polysilicon Emitter
427(1)
10.2 Design of the Base Region of a Vertical Bipolar Transistor
427(7)
10.2.1 Base Sheet Resistivity and Collector Current Density
429(1)
10.2.2 Ion-Implanted versus Epitaxially Grown Intrinsic Base
430(3)
10.2.3 General Expression for Base Transit Time
433(1)
10.3 Design of the Vertical Bipolar Transistor Collector Region
434(3)
10.3.1 Collector Design for Low-Injection Operation
435(1)
10.3.2 Collector Design for High-Injection Operation
436(1)
10.4 SiGe-Base Vertical Bipolar Transistors
437(31)
10.4.1 SiGe-Base Vertical Transistors Having Linearly Graded Base Bandgap
438(5)
10.4.2 Base Current When Ge Is Present in the Emitter
443(4)
10.4.3 Transistors Having a Trapezoidal Ge Distribution in the Base
447(4)
10.4.4 Transistors Having a Constant Ge Distribution in the Base
451(3)
10.4.5 Some Optimal Ge Profiles
454(5)
10.4.6 Base-Width Modulation by VBE
459(3)
10.4.7 Reverse-Mode I-V Characteristics
462(3)
10.4.8 Heterojunction Nature of a SiGe-Base Vertical Bipolar Transistor
465(2)
10.4.9 SiGe-Base Vertical Bipolar Transistor on Thin SOI
467(1)
10.5 Design of Symmetric Lateral Bipolar Transistors on SOI
468(11)
10.5.1 Relationship Governing Emitter-to-Collector Spacing and Base Width
470(1)
10.5.2 Analytic Model for Collector and Base Currents
471(2)
10.5.3 Analytic Ebers-Moll Model Equations
473(2)
10.5.4 Early Voltage and Emitter-Collector Spacing
475(1)
10.5.5 Analytic Model for the Transit Times
475(1)
10.5.6 On the Fabrication of Thin-Base Symmetric Lateral Transistors
476(1)
10.5.7 SiGe-on-Insulator Symmetric lateral n-p-n Transistors
477(1)
10.5.8 Symmetric Si-Emitter/Collector SiGe-Base Lateral HBT
478(1)
Exercises
479(6)
11 Bipolar Performance Factors 485(36)
11.1 Figures of Merit of a Bipolar Transistor
485(4)
11.1.1 Cutoff Frequency
486(2)
11.1.2 Maximum Oscillation Frequency
488(1)
11.1.3 Logic Gate Delay
489(1)
11.2 ECL Circuit and Delay Components
489(4)
11.2.1 Transit-Time Delay Component
491(1)
11.2.2 Intrinsic-Base-Resistance Delay Component
492(1)
11.2.3 Parasitic-Resistance Delay Components
492(1)
11.2.4 Load-Resistance Delay Component
492(1)
11.2.5 Diffusion-Capacitance Delay Component
493(1)
11.3 Speed-versus-Current Characteristics of Bipolar Transistors
493(3)
11.3.1 fT and fmax as a Function of Collector Current
493(2)
11.3.2 Logic Gate Delay as a Function of Collector Current
495(1)
11.4 Vertical-Transistor Optimization from Data Analyses
496(2)
11.5 Bipolar Device Scaling for Logic Circuits
498(4)
11.5.1 Vertical-Transistor Scaling for ECL
498(1)
11.5.2 Symmetric-Lateral-Transistor Scaling for Logic Circuits
499(1)
11.5.3 Power-Dissipation Issues with Resister-Load Bipolar Logic Circuits
500(2)
11.6 Vertical-Transistor Design Optimization for RF and Analog Circuits
502(5)
11.6.1 The Single-Transistor Amplifier
502(1)
11.6.2 Maximizing fT of a Vertical Transistor
503(1)
11.6.3 Minimizing rbi of a Vertical Transistor
504(1)
11.6.4 Maximizing fmax of a Vertical Transistor
505(1)
11.6.5 Maximizing VA of a Vertical Transistor
505(1)
11.6.6 Examples of Vertical-Transistor RF and Analog Design Tradeoffs
505(2)
11.7 Symmetric-Lateral-Transistor Design Tradeoffs and Optimization for RF and Analog Circuits
507(4)
11.7.1 Calculated Low-Injection fT and fmax of Symmetric Lateral n-p-n
507(2)
11.7.2 Fin-Structure Symmetric Lateral Transistors for fmax > 1 THz
509(1)
11.7.3 Noise Reduction with Substrate Bias
510(1)
11.8 Unique Opportunities from Symmetric Lateral Bipolar Transistors
511(6)
11.8.1 Symmetric Lateral Bipolar Transistor as a High-Drive-Current Device
511(2)
11.8.2 Revisit Integrated Injection Logic Circuits and SRAM
513(1)
11.8.3 Complementary Bipolar Logic Circuits
514(2)
11.8.4 Performance-On-Demand Designs with 12L or CBipolar Circuits
516(1)
Exercises
517(4)
12 Memory Devices 521(44)
12.1 Static Random-Access Memory
523(18)
12.1.1 CMOS SRAM Cell
523(9)
12.1.2 Other Bistable MOSFET SRAM Cells
532(1)
12.1.3 Bipolar SRAM Cell
533(8)
12.2 Dynamic Random-Access Memory
541(5)
12.2.1 Basic DRAM Cell and Its Operation
541(4)
12.2.2 Device Design and Scaling Considerations for a DRAM Cell
545(1)
12.3 Nonvolatile Memory
546(18)
12.3.1 MOSFET Nonvolatile Memory Devices
547(7)
12.3.2 Flash Memory Arrays
554(5)
12.3.3 Devices for a NOR Array
559(5)
Exercise
564(1)
References 565(22)
Index 587
Yuan Taur is a Distinguished Professor of Electrical and Computer Engineering at the University of California, San Diego, having previously worked at IBM's T. J. Watson Research Center, New York. He is an IEEE Fellow. Tak H. Ning is an IBM Fellow (Retired) at the T. J. Watson Research Center, New York. He is a Fellow of the IEEE and the American Physical Society, and a member of the US National Academy of Engineering.