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Fundamentals of Switching Theory and Logic Design: A Hands on Approach 2006 ed. [Kõva köide]

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  • Formaat: Hardback, 342 pages, kõrgus x laius: 297x210 mm, kaal: 1500 g, XIV, 342 p., 1 Hardback
  • Ilmumisaeg: 07-Mar-2006
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 0387285938
  • ISBN-13: 9780387285931
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Fundamentals of Switching Theory and Logic Design: A Hands on Approach 2006 ed.Suurem pilt
  • Formaat: Hardback, 342 pages, kõrgus x laius: 297x210 mm, kaal: 1500 g, XIV, 342 p., 1 Hardback
  • Ilmumisaeg: 07-Mar-2006
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 0387285938
  • ISBN-13: 9780387285931
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9780387285931.html
Märksõnad:
Switching theory and logic design provide mathematical foundations and tools for digital system design that is an essential part in the research and development in almost all areas of modern technology. The vast complexity of modern digital systems implies that they can only be handled by computer aided design tools that are built on sophisticated mathematical models. Fundamentals of Switching Theory and Logic Design is aimed at providing an accessible introduction to these mathematical techniques that underlie the design tools and that are necessary for understanding their capabilities and limitations.



As is typical to many disciplines a high level of abstraction enables a unified treatment of many methodologies and techniques as well as provides a deep understanding of the subject in general. The drawback is that without a hands-on touch on the details it is difficult to develop an intuitive understanding of the techniques. We try to combine these views by providing hands-on examples on the techniques while binding these to the more general theory that is developed in parallel. For instance, the use of vector spaces and group theory unifies the spectral (Fourier-like) interpretation of polynomial, and graphic (decision diagrams) representations of logic functions, as well as provides new methods for optimization of logic functions.



Consequently, Fundamentals of Switching Theory and Logic Design discusses the fundamentals of switching theory and logic design from a slightly alternative point of view and also presents links between switching theory and related areas of signal processing and system theory. It also covers the core topics recommended in IEEE/ACM curricula for teaching and study in this area. Further, it contains several elective sections discussing topics for further research work in this area
Preface xi
Acronyms xiii
1. SETS, RELATIONS, LOGIC FUNCTIONS
1(20)
1 Sets
1(1)
2 Relations
2(2)
3 Functions
4(5)
4 Representations of Logic Functions
9(8)
4.1 SOP and POS expressions
13(3)
4.2 Positional Cube Notation
16(1)
5 Factored Expressions
17(2)
6 Exercises and Problems
19(2)
2. ALGEBRAIC STRUCTURES FOR LOGIC DESIGN
21(26)
1 Algebraic Structure
21(1)
2 Finite Groups
21(3)
3 Finite Rings
24(1)
4 Finite Fields
25(2)
5 Homomorphisms
27(3)
6 Matrices
30(3)
7 Vector spaces
33(4)
8 Algebra
37(1)
9 Boolean Algebra
38(6)
9.1 Boolean expressions
40(2)
10 Graphs
42(2)
11 Exercises and Problems
44(3)
3. FUNCTIONAL EXPRESSIONS FOR SWITCHING FUNCTIONS
47(42)
1 Shannon Expansion Rule
50(1)
2 Reed-Muller Expansion Rules
51(5)
3 Fast Algorithms for Calculation of RM-expressions
56(1)
4 Negative Davio Expression
57(2)
5 Fixed Polarity Reed-Muller Expressions
59(3)
6 Algebraic Structures for Reed-Muller Expressions
62(1)
7 Interpretation of Reed-Muller Expressions
63(1)
8 Kronecker Expressions
64(4)
8.1 Generalized bit-level expressions
67(1)
9 Word-Level Expressions
68(19)
9.1 Arithmetic expressions
70(3)
9.2 Calculation of Arithmetic Spectrum
73(1)
9.3 Applications of AR,s
74(3)
10 Walsh Expressions
77(3)
11 Walsh Functions and Switching Variables
80(1)
12 Walsh Series
80(2)
13 Relationships Among Expressions
82(3)
14 Generalizations to Multiple-Valued Functions
85(2)
15 Exercises and Problems
87(2)
4. DECISION DIAGRAMS FOR REPRESENTATION OF SWITCHING FUNCTIONS
89(36)
1 Decision Diagrams
89(8)
2 Decision Diagrams over Groups
97(2)
3 Construction of Decision Diagrams
99(3)
4 Shared Decision Diagrams
102(1)
5 Multi-terminal binary decision diagrams
103(1)
6 Functional Decision Diagrams
103(5)
7 Kronecker decision diagrams
108(2)
8 Pseudo-Kronecker decision diagrams
110(2)
9 Spectral Interpretation of Decision Diagrams
112(7)
9.1 Spectral transform decision diagrams
112(2)
9.2 Arithmetic spectral transform decision diagrams
114(1)
9.3 Walsh decision diagrams
115(4)
10 Reduction of Decision Diagrams
119(3)
11 Exercises and Problems
122(3)
5. CLASSIFICATION OF SWITCHING FUNCTIONS
125(22)
1 NPN-classification
126(3)
2 SD-Classification
129(4)
3 LP-classification
133(4)
4 Universal Logic Modules
137(8)
5 Exercises and Problems
145(2)
6. SYNTHESIS WITH MULTIPLEXERS
147(24)
1 Synthesis with Multiplexers
149(8)
1.1 Optimization of Multiplexer Networks
151(2)
1.2 Networks with Different Assignments of Inputs
153(1)
1.3 Multiplexer Networks from BDD
154(3)
2 Applications of Multiplexers
157(5)
3 Demultiplexers
162(1)
4 Synthesis with Demultiplexers
162(4)
5 Applications of Demultiplexers
166(2)
6 Exercises and Problems
168(3)
7. REALIZATIONS WITH ROM
171(12)
1 Realizations with ROM
171(5)
2 Two-level Addressing in ROM Realizations
176(4)
3 Characteristics of Realizations with ROM
180(1)
4 Exercises and Problems
181(2)
8. REALIZATIONS WITH PROGRAMMABLE LOGIC ARRAYS
183(16)
1 Realizations with PLA
184(2)
2 The optimization of PLA
186(3)
3 Two-level Addressing of PLA
189(2)
4 Folding of PLA
191(3)
5 Minimization of PLA by Characteristic Functions
194(2)
6 Exercises and Problems
196(3)
9. UNIVERSAL CELLULAR ARRAYS
199(12)
1 Features of Universal Cellular Arrays
199(2)
2 Realizations with Universal Cellular Arrays
201(4)
3 Synthesis with Macro Cells
205(3)
4 Exercises and Problems
208(3)
10. FIELD PROGRAMMABLE LOGIC ARRAYS 211(24)
1 Synthesis with FPGAs
221(1)
2 Synthesis with Antifuse-Based FPGAs
222(2)
3 Synthesis with LUT-FPGAs
224(1)
3.1 Design procedure
225(8)
4 Exercises and Problems
233(2)
11. BOOLEAN DIFFERENCE AND APPLICATIONS IN TESTING LOGIC NETWORKS 235(34)
1 Boolean difference
236(1)
2 Properties of the Boolean Difference
237(1)
3 Calculation of the Boolean Difference
238(4)
4 Boolean Difference in Testing Logic Networks
242(8)
4.1 Errors in combinatorial logic networks
242(4)
4.2 Boolean difference in generation of test sequences
246(4)
5 Easily Testable Logic Networks
250(1)
5.1 Features of Easily Testable Networks
251(1)
6 Easily Testable Realizations from PPRM-expressions
251(6)
7 Easily Testable Realizations from GRM-expressions
257(8)
7.1 Related Work, Extensions, and Generalizations
263(2)
8 Exercises and Problems
265(4)
12. SEQUENTIAL NETWORKS 269(28)
1 Basic Sequential Machines
271(3)
2 State Tables
274(3)
3 Conversion of Sequential Machines
277(1)
4 Minimization of States
278(3)
5 Incompletely Specified Machines
281(2)
6 State Assignment
283(4)
7 Decomposition of Sequential Machines
287(7)
7.1 Serial Decomposition of Sequential Machines
287(3)
7.2 Parallel Decomposition of Sequential Machines
290(4)
8 Exercises and Problems
294(3)
13. REALIZATION OF SEQUENTIAL NETWORKS 297(28)
1 Memory Elements
298(4)
2 Synthesis of Sequential Networks
302(2)
3 Realization of Binary Sequential Machines
304(2)
4 Realization of Synchronous Sequential Machines
306(3)
5 Pulse Mode Sequential Networks
309(4)
6 Asynchronous Sequential Networks
313(5)
7 Races and Hazards
318(4)
7.1 Race
319(1)
7.2 Hazards
320(2)
8 Exercises and Problems
322(3)
References 325(14)
Index 339


Radomir Stankovic received the B.Sc. degree in electronic engineering from the Faculty of Electronics, University of Ni v, Serbia, Yugoslavia in 1976, and M.Sc. and Ph.D. degrees in applied mathematics from the Faculty of Electrical Engineering, University of Belgrade, Serbia, Yugoslavia, in 1984 and 1986, respectively. Currently, he is a Professor at Department of Computer Science, University of Ni v, Serbia, Yugoslavia. His research interests include spectral techniques, switching theory and multiple-valued logic, and signal processing. He is a member of IEICE.



Jaakko Astola (Fellow IEEE) received B.Sc., M.S.c, Licentiate and Ph.D. degrees in mathematics (specializing in error-correcting codes) from Turku University, Finland, in 1972, 1973, 1975, and 1978 respectively. From 1993 he has been Professor of Signal Processing and Director of Tampere International Center for Signal Processing leading a group of about 60 scientists and was nominated Academy Professor by Academy of Finland (2001-2006). His research interests include signal processing, coding theory, spectral techniques and statistics.