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Gate Dielectric Integrity: Material, Process and Tool Qualification: Material, Process and Tool Qualification [Pehme köide]

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  • Formaat: Paperback / softback, 176 pages, kõrgus x laius x paksus: 222x152x13 mm, kaal: 272 g
  • Ilmumisaeg: 01-Jan-2000
  • Kirjastus: American Society for Testing & Materials
  • ISBN-10: 0803126158
  • ISBN-13: 9780803126152
  • Formaat: Paperback / softback, 176 pages, kõrgus x laius x paksus: 222x152x13 mm, kaal: 272 g
  • Ilmumisaeg: 01-Jan-2000
  • Kirjastus: American Society for Testing & Materials
  • ISBN-10: 0803126158
  • ISBN-13: 9780803126152
Contains papers from a January 1999 conference held in San Jose, California, describing concepts and metrology of Gate Dielectric Integrity (GDI) and discussing its applications for material and device processes and tool qualification. Topics include methods, protocols, and reliability assessment as related to dielectric integrity. Papers are organized in sections on concepts, thin gate dielectrics, characterization and applications, and standardization. There is also a section summarizing panel discussions. Gupta is affiliated with Mitsubishi Silicon America. Brown is affiliated with Texas Instruments Inc. Annotation c. Book News, Inc., Portland, OR (booknews.com)
Overview ix Dinesh C. Gupta George A. Brown Concepts Gate Oxide Reliability Assessment and Some Connections to Oxide Integrity 3(24) D. J. Dumin Thin Gate Dielectrics Ultra-Thin Film Dielectrics Reliability Characterization 27(14) J. S. Suehle Voltage Step Stress for 10 nm Oxides 41(6) A. Strong Localized Charging Damage in Thin Oxides 47(18) G. Bersuker J. Werking Characterization and Applications Characterization of Gate Dielectrics With Mercury Gate MOS Current-Voltage Measurements 65(9) G. A. Gruber R. J. Hillard COCOS (Corona Oxide Characterization of Semiconductor) Metrology: Physical Principal and Applications 74(17) M. Wilson J. Lagowski A. Savtchouk L. Jastrzebski J. D Amico. Application of Quantox Measurements to Identify Phosphorus Contamination in Silicon Wafers 91(11) M. A. Dexter K. M. Hasslinger J. R. Fritz C. A. Ullo Applications of Gate Oxide Integrity Measurements in Silicon Wafer Manufacturing 102(10) M. R. Seacrist Silicon Substrate Related Gate Oxide Integrity at Different Oxide Thicknesses 112(10) E. D. Grann A. Huber J. Grabmeier R. Holzi R. Wahlich Single Wafer Gate Dielectric Technologies for Sub-0.18 μm Applications 122(10) G. Miner G. Xing Y. Yokota A. Jaggi E. Sanchez C. Chen D. Lopez High Resolution Gate Oxide Integrity (GOI) Measurement in Near-Perfect Silicon 132(13) Y. Murakami T. Yamazaki W. Itou T. Shingyouji Qualification of Epi Layers and Interface Properties by an Improved μ-PCD Technique 145 T. Pavelka Standardization and Round Robins Appendix 1---Interim Reports of Two Inter-Laboratory Round Robins on Gate Oxide Integrity, One Conducted by ASTM Committee F-1 and JEDEC Committee, and the Other Conducted by JEIDA Committee and SEMI, Japan 157 Panel Discussions Appendix 2---Panel Discussion---A Synopsis 167