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Handbook of FPGA Design Security 2010 [Kõva köide]

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  • Formaat: Hardback, 177 pages, kõrgus x laius: 235x155 mm, kaal: 1000 g, XVIII, 177 p., 1 Hardback
  • Ilmumisaeg: 05-Jul-2010
  • Kirjastus: Springer
  • ISBN-10: 9048191564
  • ISBN-13: 9789048191567
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Handbook of FPGA Design Security 2010Suurem pilt
  • Formaat: Hardback, 177 pages, kõrgus x laius: 235x155 mm, kaal: 1000 g, XVIII, 177 p., 1 Hardback
  • Ilmumisaeg: 05-Jul-2010
  • Kirjastus: Springer
  • ISBN-10: 9048191564
  • ISBN-13: 9789048191567
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9789048191567.html
Märksõnad:
The Purpose of Handbook of FPGA Design Security is to provide a practical approach to managing security in FPGA designs for researchers and practitioners in the electronic dessign automation (EDA) and FPGA communities, including corporations, industrial and government research labs, and academics. Handbook of FPGA Design Security combines theoretical underpinnings with a practical design approach and worked examples for combating real world theats. To address the spectrum of lifecycle and operational threats against FPGA systems, a holistic view of FPGA security is presented, from formal top level specification to low level policy enforcement mechanisms. This perspective integrates recent advances in the fields of computer security theory, languages, compilers, and hardware. The net effect is a diverse set of static and runtime techniques that, working in cooperation, facilitate the composition of robust, dependable, and trustworthy systems using commodity components.

The purpose of Handbook of FPGA Design Security is to provide a practical approach to managing security in FPGA designs for researchers and practitioners in the electronic design automation (EDA) and FPGA communities, including corporations, industrial and government research labs, and academics. Handbook of FPGA Design Security combines theoretical underpinnings with a practical design approach and worked examples for combating real world threats. To address the spectrum of lifecycle and operational threats against FPGA systems, a holistic view of FPGA security is presented, from formal top level specification to low level policy enforcement mechanisms. This perspective integrates recent advances in the fields of computer security theory, languages, compilers, and hardware. The net effect is a diverse set of static and runtime techniques that, working in cooperation, facilitate the composition of robust, dependable, and trustworthy systems using commodity components.

This book offers a practical approach to managing security in FPGA designs for researchers and practitioners in the electronic design automation (EDA) and FPGA communities, including corporations, industrial and government research labs, and academics.
1 Introduction and Motivation
1(26)
1.1 The Growing Reliance on FPGAs
1(5)
1.1.1 FPGAs for Aerospace
2(2)
1.1.2 FPGAs for Supercomputing
4(1)
1.1.3 FPGAs for Video Analysis
5(1)
1.1.4 FPGAs for High-Throughput Cryptography
5(1)
1.1.5 FPGAs for Intrusion Detection and Prevention
6(1)
1.2 FPGA Architectures
6(10)
1.2.1 The Attractiveness of Reconfigurable Hardware
7(1)
1.2.2 The Internals of an FPGA
8(5)
1.2.3 Design Flow
13(3)
1.3 The Many Facets of FPGA Security
16(5)
1.3.1 Security is Hard
17(1)
1.3.2 Complexity and Abstraction
18(1)
1.3.3 Baked in Versus Tacked on
19(1)
1.3.4 Separation of FPGA Cores
20(1)
1.4 Organization of This Book
21(6)
References
22(5)
2 High Assurance Software Lessons and Techniques
27(44)
2.1 Background
27(1)
2.2 Malicious Software
27(3)
2.2.1 Trojan Horses
28(1)
2.2.2 Subversion
29(1)
2.3 Assurance
30(1)
2.4 Commensurate Protection
31(3)
2.4.1 Threat Model
32(2)
2.5 Security Policy Enforcement
34(17)
2.5.1 Types of Policies
34(5)
2.5.2 Policy Enforcement Mechanisms
39(11)
2.5.3 Composition of Trusted Components
50(1)
2.6 Assurance of Policy Enforcement
51(20)
2.6.1 Life Cycle Support
52(3)
2.6.2 Configuration Management
55(1)
2.6.3 Independent Assessment
56(2)
2.6.4 Dynamic Program Analysis
58(2)
2.6.5 Trusted Distribution
60(1)
2.6.6 Trusted Recovery
61(1)
2.6.7 Static Analysis of Program Specifications
62(3)
References
65(6)
3 Hardware Security Challenges
71(16)
3.1 Malicious Hardware
71(4)
3.1.1 Categories of Malicious Hardware
71(1)
3.1.2 Foundry Trust
72(2)
3.1.3 Physical Attacks
74(1)
3.2 Covert Channel Definition
75(3)
3.2.1 The Process Abstraction
76(1)
3.2.2 Equivalence Classes
76(1)
3.2.3 Formal Definition
76(1)
3.2.4 Synchronization
77(1)
3.2.5 Shared Resources
77(1)
3.2.6 Requirements
77(1)
3.2.7 Bypass
78(1)
3.3 Existing Approaches to Limiting Covert and Side Channel Attacks
78(2)
3.3.1 Shared Resource Matrix Methodology
78(1)
3.3.2 Cache Interference
79(1)
3.3.3 FPGA Masking Schemes
79(1)
3.4 Detecting and Mitigating Covert Channels on FPGAs
80(1)
3.4.1 Design Flows
80(1)
3.4.2 Spatial Isolation
80(1)
3.4.3 Memory Protection
81(1)
3.5 Policy State as a Covert Storage Channel
81(6)
3.5.1 Stateful Policies
81(1)
3.5.2 Covert Channel Mechanism
81(1)
3.5.3 Encoding Schemes
82(1)
3.5.4 Covert Storage Channel Detection
83(1)
3.5.5 Covert Channel Mitigation
83(1)
References
84(3)
4 FPGA Updates and Programmability
87(10)
4.1 Introduction
87(1)
4.2 Bitstream Encryption and Authentication
87(3)
4.2.1 Key Management
88(1)
4.2.2 Defeating Bitstream Encryption
89(1)
4.3 Remote Updates
90(1)
4.3.1 Authentication
90(1)
4.3.2 Trusted Recovery
91(1)
4.4 Partial Reconfiguration
91(6)
4.4.1 Applications of Partial Reconfiguration
91(1)
4.4.2 Hot-Swappable vs. Stop-the-World
92(1)
4.4.3 Internal Configuration Access Port
92(1)
4.4.4 Dynamic Security and Complexity
92(1)
4.4.5 Object Reuse
93(1)
4.4.6 Integrity Verification
94(1)
References
95(2)
5 Memory Protection on FPGAs
97(30)
5.1 Overview
97(1)
5.2 Memory Protection on FPGAs
98(1)
5.3 Policy Description and Policy
99(5)
5.3.1 Memory Access Policy
99(3)
5.3.2 Hardware Synthesis
102(2)
5.4 A Higher-Level Specification Language
104(2)
5.5 Example Policies
106(10)
5.5.1 Controlled Sharing
106(2)
5.5.2 Access List
108(1)
5.5.3 Chinese Wall
109(1)
5.5.4 Bell and LaPadula Confidentiality Model
110(1)
5.5.5 High Water Mark
111(1)
5.5.6 Biba Integrity Model
112(1)
5.5.7 Redaction
113(3)
5.6 System Architecture
116(1)
5.7 Evaluation
116(1)
5.8 Using the Policy Compiler
117(3)
5.9 Constructing Mathematically Precise Policies
120(5)
5.9.1 Cross Product Method
120(1)
5.9.2 Examples
121(2)
5.9.3 Monotonic Policy Changes
123(1)
5.9.4 Formal Aspects of Hybrid Policies
124(1)
5.10 Summary
125(2)
References
125(2)
6 Spatial Separation with Moats
127(12)
6.1 Overview
127(1)
6.2 Separation
128(1)
6.3 Physical Isolation with Moats
128(1)
6.4 Construction Moats
128(4)
6.4.1 The Gap Method
129(1)
6.4.2 The Inspection Method
130(1)
6.4.3 Comparing the Gap and Inspection Methods
130(2)
6.5 Secure Interconnect with Drawbridges
132(5)
6.5.1 Drawbridges for Direct Connections
132(3)
6.5.2 Route Tracing with Partial Reconfiguration
135(1)
6.5.3 Drawbridges for Shared Bus Architectures
135(2)
6.6 Protecting the Reference Monitor with Moats
137(2)
References
138(1)
7 Putting it all Together: A Design Example
139(14)
7.1 A Multi-Core Reconfigurable Embedded System
139(1)
7.2 On-Chip Peripheral Bus
140(1)
7.3 AES core
141(1)
7.4 Logical Isolation Compartments
141(1)
7.5 Reference Monitor
141(1)
7.6 Stateful Policy
142(3)
7.7 Secure Interconnect Scalability
145(1)
7.8 Covert Channels
145(1)
7.9 Incorporating Moats and Drawbridges
146(1)
7.10 Implementation and Evaluation
147(1)
7.11 Software Interface
148(1)
7.12 Security Usability
148(1)
7.13 More Example Security Architectures
148(3)
7.13.1 Classes of Designs
148(2)
7.13.2 Topologies
150(1)
7.14 Summary
151(2)
References
152(1)
8 Forward-Looking Problems
153(8)
8.1 Trustworthy Tools
153(1)
8.2 Formal Verification of Secure Systems
154(1)
8.3 Security Usability
155(1)
8.4 Hardware Trust
155(1)
8.5 Languages
155(1)
8.6 Configuration Management
156(1)
8.7 Securing the Supply Chain
156(1)
8.8 Physical Attacks on FPGAs
157(1)
8.9 Design Theft and Failure Analysis
157(1)
8.10 Partial Reconfiguration and Dynamic Security
158(1)
8.11 Concluding Remarks
158(3)
References
160(1)
A Computer Architecture Fundamentals
161(14)
A.1 What do Computer Architects do all Day?
161(1)
A.2 Tradeoffs Between CPUs, FPGAs, and ASICs
162(1)
A.3 Computer Architecture and Computer Science
163(1)
A.4 Program Analysis
164(4)
A.4.1 The Science of Processor Simulation
164(1)
A.4.2 On-Chip Profiling Engines
165(1)
A.4.3 Binary Instrumentation
166(1)
A.4.4 Phase Classification
167(1)
A.5 Novel Computer Architectures
168(2)
A.5.1 The DIVA Architecture
168(1)
A.5.2 The Raw Microprocessor
169(1)
A.5.3 The WaveScalar Architecture
169(1)
A.5.4 Architectures for Medicine
169(1)
A.6 Memory
170(3)
A.7 Superscalar Processors
173(1)
A.8 Multithreading
174(1)
References 175