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Handbook of Magnetic Random Access Memory [Kõva köide]

  • Formaat: Hardback, 304 pages, kõrgus x laius: 234x156 mm, 120 Illustrations, black and white; 120 Illustrations, black and white
  • Ilmumisaeg: 01-Jan-2025
  • Kirjastus: Productivity Press
  • ISBN-10: 1498754694
  • ISBN-13: 9781498754699
Handbook of Magnetic Random Access Memory
  • Formaat: Hardback, 304 pages, kõrgus x laius: 234x156 mm, 120 Illustrations, black and white; 120 Illustrations, black and white
  • Ilmumisaeg: 01-Jan-2025
  • Kirjastus: Productivity Press
  • ISBN-10: 1498754694
  • ISBN-13: 9781498754699

Spintronics is a promising technology as one of the alternatives to the traditional memory technology. MRAM is one of the major applications of Spintronics. The authors offer the first comprehensive book on MRAM.  It is structured to be a complete and updated guide for the readers. This book provides an overview of the state of the art, describes industrial applications, and presents original technologies in this rapidly-moving field. It covers aspects from physics, device, circuit, and system to application of MRAM. The book provides the necessary skills, tools and guidelines for different-level MRAM designers. It also summarizes the challenges and prospects of MRAM.

1.2 Challenges of conventional memory technologies 1.3 Non-volatile memory technologies 1.4 State of the art (roadmap)2. Spintronics fundamentals 2.1 General principles 2.2 Giant MagnetoResistance (GMR) and Magnetic Tunnel MagnetoResistance (TMR) 2.3 Perpendicular Magnetic Anisotropy 2.4 Spin Transfer Torque (STT) and Spin Hall Effect (SHE) 2.5 Emerging spin related phenomena for MRAM3. MRAM 3.1 Field-MRAM 3.2 STT-MRAM 3.3 SHE-MRAM 3.4 Racetrack Memory 3.5 Advanced MRAM concepts4. Device Fabrication 4.1 Introduction of processing tools 4.2 Ultra-thin film deposition 4.3 Nanopillar processing 4.4 Back-end integration with CMOS technology 4.5 Device fabrication status and challenges5. Circuit and architecture designs 5.1 Device modeling and EDA tools for hybrid simulation 5.2 Cell structure and array organization 5.3 Cell Read/write techniques and Error Correction Code 5.4 Memory Chip architecture design 5.5 Circuit and architecture design status and challenges6 Performance evaluation for potential applications