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Hands-On Guide to Designing Embedded Systems Unabridged edition [Kõva köide]

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  • Formaat: Hardback, 252 pages, Illustrations
  • Ilmumisaeg: 31-Oct-2021
  • Kirjastus: Artech House Publishers
  • ISBN-10: 1630816833
  • ISBN-13: 9781630816834
Teised raamatud teemal:
Hands-On Guide to Designing Embedded Systems Unabridged editionSuurem pilt
  • Formaat: Hardback, 252 pages, Illustrations
  • Ilmumisaeg: 31-Oct-2021
  • Kirjastus: Artech House Publishers
  • ISBN-10: 1630816833
  • ISBN-13: 9781630816834
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781630816834.html
Märksõnad:
This practical resource introduces readers to the design of field programmable gate array systems (FPGAs). Techniques and principles that can be applied by the engineer to understand challenges before starting a project are presented. The book provides a framework from which to work and approach development of embedded systems that will give readers a better understanding of the issues at hand and can develop solution which presents lower technical and programmatic risk and a faster time to market.





Programmatic and system considerations are introduced, providing an overview of the engineering life cycle when developing an electronic solution from concept to completion. Hardware design architecture is discussed to help develop an architecture to meet the requirements placed upon it, and the trade-offs required to achieve the budget. The FPGA development lifecycle and the inputs and outputs from each stage, including design, test benches, synthesis, mapping, place and route and power estimation, are also presented. Finally, the importance of reliability, why it needs to be considered, the current standards that exist, and the impact of not considering this is explained. Written by experts in the field, this is the first book by "engineers in the trenches" that presents FPGA design on a practical level.
Acknowledgments xi
Introduction xv
Chapter 1 Programmatic and System-Level Considerations 1(52)
1.1 Introduction: SensorsThink
1(1)
1.2 Product Development Stages
2(3)
1.3 Product Development Stages: Tailoring
5(1)
1.4 Product Development: After Launch
6(1)
1.5 Requirements
7(9)
1.5.1 The V-Model
10(2)
1.5.2 SensorsThink: Product Requirements
12(1)
1.5.3 Creating Useful Requirements
13(3)
1.5.4 Requirements: Finishing Up
16(1)
1.6 Architectural Design
16(17)
1.6.1 SEBoK: An Invaluable Resource
17(3)
1.6.2 SensorsThink: Back to the Journey
20(1)
1.6.3 Systems Engineering: An Overview
21(2)
1.6.4 Architecting the System, Logically
23(1)
1.6.5 Keep Things in Context (Diagrams)
24(2)
1.6.6 Monitor Your Activity (Diagrams)
26(2)
1.6.7 Know the Proper Sequence (Diagrams)
28(1)
1.6.8 Architecting the System Physically
28(1)
1.6.9 Physical Architecture: Playing with Blocks
29(2)
1.6.10 Trace Your Steps
31(1)
1.6.11 System Verification and Validation: Check Your Work
32(1)
1.7 Engineering Budgets
33(5)
1.7.1 Types of Budgets
33(1)
1.7.2 Engineering Budgets: Some Examples
34(4)
1.7.3 Engineering Budgets: Finishing Up
38(1)
1.8 Interface Control Documents
38(4)
1.8.1 Sticking Together: Signal Grouping
39(2)
1.8.2 Playing with Legos: Connectorization
41(1)
1.8.3 Talking Among Yourselves: Internal ICDs
42(1)
1.9 Verification
42(5)
1.9.1 Verifying Hardware
43(1)
1.9.2 How Much Testing Is Enough?
43(1)
1.9.3 Safely Navigating the World of Testing
44(1)
1.9.4 A Deeper Dive into Derivation (of Test Cases)
45(2)
1.10 Engineering Governance
47(3)
1.10.1 Not Just Support for Design Reviews
48(1)
1.10.2 Engineering Rule Sets
48(1)
1.10.3 Compliance
49(1)
1.10.4 Review Meetings
49(1)
References
50(3)
Chapter 2 Hardware Design Considerations 53(70)
2.1 Component Selection
53(13)
2.1.1 Key Component Identification for the SoC Platform
53(4)
2.1.2 Key Component Selection Example: The SoC
57(6)
2.1.3 Key Component Selection Example: Infrared Sensor
63(2)
2.1.4 Key Component Selection: Finishing Up
65(1)
2.2 Hardware Architecture
66(6)
2.2.1 Hardware Architecture for the SoC Platform
66(4)
2.2.2 Hardware Architecture: Interfaces
70(2)
2.2.3 Hardware Architecture: Data Flows
72(1)
2.2.4 Hardware Architecture: Finishing Up
72(1)
2.3 Designing the System
72(6)
2.3.1 What to Worry About
73(1)
2.3.2 Power Supply Analysis, Architecture, and Simulation
73(1)
2.3.3 Processor and FPGA Pinout Assignments
74(1)
2.3.4 System Clocking Requirements
75(1)
2.3.5 System Reset Requirements
75(1)
2.3.6 System Programming Scheme
75(1)
2.3.7 Summary
76(1)
2.3.8 Example: Zynq Power Sequence Requirements
76(2)
2.4 Decoupling Your Components
78(4)
2.4.1 Decoupling: By the Book
78(1)
2.4.2 To Understand the Component, You Must Be the Component
78(1)
2.4.3 Types of Decoupling
79(1)
2.4.4 Example: Zynq-7000 Decoupling
80(1)
2.4.5 Additional Thoughts: Specialized Decoupling
81(1)
2.4.6 Additional Thoughts: Simulation
81(1)
2.5 Connect with Your System
82(5)
2.5.1 Contemplating Connectors
82(1)
2.5.2 Example: System Communications
83(4)
2.6 Extend the Life of the System: De-Rate
87(3)
2.6.1 Why De-Rate?
87(1)
2.6.2 What Can Be De-Rated?
87(2)
2.6.3 Example: De-Rating the Zynq-7000
89(1)
2.6.4 Additional Thoughts: Exceptions to the Rule
89(1)
2.7 Test, Test, Test
90(7)
2.7.1 Back to Basics: Pre-Power-On Checklist
90(3)
2.7.2 Check for Signs of Life: Crawl Before Walking
93(1)
2.7.3 Roll Up Your Sleeves and Get Ready to Run
94(1)
2.7.4 Example: I2C Interface
95(2)
2.7.5 Additional Thoughts
97(1)
2.8 Integrity: Important for Electronics
97(7)
2.8.1 Power Integrity
98(1)
2.8.2 Signal Integrity
98(1)
2.8.3 Digging Deeper into Power Integrity
99(1)
2.8.4 Digging Deeper into Signal Integrity
100(2)
2.8.5 Example: ULPI Pre-Layout Analysis
102(2)
2.8.6 Suggested Additional Reading
104(1)
2.9 PCB Layout: Not for the Faint of Heart
104(16)
2.9.1 Floor Planning
106(2)
2.9.2 Follow the Rats
108(2)
2.9.3 Mechanical Constraints
110(1)
2.9.4 Electrical Constraints
111(2)
2.9.5 Stack-Up Design
113(6)
2.9.6 Experience Matters
119(1)
References
120(3)
Chapter 3 FPGA Design Considerations 123(76)
3.1 Introduction
123(1)
3.2 FPGA Development Process
124(6)
3.2.1 Introduction to the Target Device
126(1)
3.2.2 FPGA Requirements
127(2)
3.2.3 FPGA Architecture
129(1)
3.3 Accelerating Design Using IP Libraries
130(1)
3.4 Pin Planning and Constraints
131(9)
3.4.1 Physical Constraints
134(3)
3.4.2 Timing Constraints
137(1)
3.4.3 Timing Exceptions
138(1)
3.4.4 Physical Constraints: Placement
139(1)
3.5 Clock Domain Crossing
140(3)
3.6 Test Bench and Verification
143(5)
3.6.1 What Is Verification?
143(1)
3.6.2 Self-Checking Test Benches
144(1)
3.6.3 Corner Cases, Boundary Conditions, and Stress Testing
145(1)
3.6.4 Code Coverage
146(1)
3.6.5 Test Functions and Procedures
146(1)
3.6.6 Behavioral Models
147(1)
3.6.7 Using Text IO Files
147(1)
3.6.8 What Else Might We Consider?
148(1)
3.7 Finite State Machine Design
148(9)
3.7.1 Defining a State Machine
148(1)
3.7.2 Algorithmic State Diagrams
149(1)
3.7.3 Moore or Mealy: What Should I Choose?
149(1)
3.7.4 Implementing the State Machine
150(1)
3.7.5 State Machine Encoding
151(2)
3.7.6 Increasing Performance of State Machines
153(2)
3.7.7 Good Design Practices for FPGA Implementation
155(1)
3.7.8 FLIR Lepton Interface
155(2)
3.8 Defensive State Machine Design
157(5)
3.8.1 Detection Schemes
157(2)
3.8.2 Hamming Schemes
159(1)
3.8.3 Deadlock and Other Issues
160(1)
3.8.4 Implementing Defensive State Machines in Xilinx Devices
161(1)
3.9 How Does FPGA Do Math?
162(1)
3.9.1 Representation of Numbers
162(1)
3.10 Fixed Point Mathematics
163(7)
3.10.1 Fixed-Point Rules
164(2)
3.10.2 Overflow
166(1)
3.10.3 Real-World Implementation
167(2)
3.10.4 RTL Implementation
169(1)
3.11 Polynomial Approximation
170(3)
3.11.1 The Challenge with Some Algorithms
171(1)
3.11.2 Capitalize on FPGA Resources
172(1)
3.11.3 Multiple Trend Lines Selected by Input Value
173(1)
3.12 The CORDIC Algorithm
173(3)
3.13 Convergence
176(1)
3.14 Where Are These Used?
176(1)
3.15 Modeling in Excel
176(1)
3.16 Implementing the CORDIC
177(2)
3.17 Digital Filter Design and Implementation
179(5)
3.17.1 Filter Types and Topologies
179(2)
3.17.2 Frequency Response
181(1)
3.17.3 Impulse Response
181(1)
3.17.4 Step Response
182(1)
3.17.5 Windowing the Filter
182(2)
3.18 Fast Fourier Transforms
184(1)
3.18.1 Time or Frequency Domain?
184(1)
3.19 How Do We Get There?
184(5)
3.19.1 Where Do We Use These?
186(1)
3.19.2 FPGA-Based Implementation
186(2)
3.19.3 Higher-Speed Sampling
188(1)
3.20 Working with ADC and DAC
189(4)
3.20.1 ADC and DAC Key Parameters
189(2)
3.20.2 The Frequency Spectrum
191(1)
3.20.3 Communication
191(1)
3.20.4 DAC Filtering
192(1)
3.20.5 In-System Test
192(1)
3.21 High-Level Synthesis
193(6)
Chapter 4 When Reliability Counts 199(41)
4.1 Introduction to Reliability
199(2)
4.2 Mathematical Interpretation of System Reliability
201(9)
4.2.1 The Bathtub Curve
202(1)
4.2.2 Failure Rate (A)
202(2)
4.2.3 Early Life Failure Rate
204(1)
4.2.4 Key Terms
205(1)
4.2.5 Repairable and Nonrepairable Systems
206(1)
4.2.6 MTTF, MTBF, and MTTR
206(2)
4.2.7 Maintainability
208(1)
4.2.8 Availability
209(1)
4.3 Calculating System Reliability
210(6)
4.3.1 Scenario 1: All Critical Components Connected in Series
212(3)
4.3.2 Scenario 2: All Critical Components Connected in Parallel
215(1)
4.3.3 Scenario 3: All Critical Components Are Connected in Series-Parallel Configuration
216(1)
4.4 Faults, Errors, and Failure
216(5)
4.4.1 Classification of Faults
218(1)
4.4.2 Fault Prevention Versus Fault Tolerance: Which One Can Address System Failure Better?
219(2)
4.5 Fault Tolerance Techniques
221(6)
4.5.1 Redundancy Technique for Hardware Fault Tolerance
223(1)
4.5.2 Software Fault Tolerance
224(3)
4.6 Worst-Case Circuit Analysis
227(13)
4.6.1 Sources of Variation
230(3)
4.6.2 Numerical Analysis Using SPICE Modeling
233(7)
Selected Bibliography 240(1)
About the Authors 241(2)
Index 243