Hardware Accelerator Systems for Artificial Intelligence and Machine Learning, Volume 122 delves into arti cial Intelligence and the growth it has seen with the advent of Deep Neural Networks (DNNs) and Machine Learning. Updates in this release include chapters on Hardware accelerator systems for artificial intelligence and machine learning, Introduction to Hardware Accelerator Systems for Artificial Intelligence and Machine Learning, Deep Learning with GPUs, Edge Computing Optimization of Deep Learning Models for Specialized Tensor Processing Architectures, Architecture of NPU for DNN, Hardware Architecture for Convolutional Neural Network for Image Processing, FPGA based Neural Network Accelerators, and much more.
- Updates on new information on the architecture of GPU, NPU and DNN
- Discusses In-memory computing, Machine intelligence and Quantum computing
- Includes sections on Hardware Accelerator Systems to improve processing efficiency and performance
| Contributors |
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ix | |
| Preface |
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xi | |
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1 Introduction to hardware accelerator systems for artificial intelligence and machine learning |
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1 | (22) |
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1 Introduction to artificial intelligence and machine learning in hardware acceleration |
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2 | (2) |
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2 Deep learning and neural network acceleration |
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4 | (4) |
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3 HW accelerators for artificial neural networks and machine learning |
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8 | (5) |
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4 SW framework for deep neural networks |
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13 | (3) |
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5 Comparison of FPGA, CPU and GPU |
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16 | (3) |
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6 Conclusion and future scope |
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19 | (1) |
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19 | (2) |
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21 | (2) |
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2 Hardware accelerator systems for embedded systems |
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23 | (28) |
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24 | (2) |
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2 Neural network computing in embedded systems |
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26 | (8) |
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3 Hardware acceleration in embedded systems |
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34 | (8) |
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4 Software frameworks for neural networks |
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42 | (2) |
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44 | (1) |
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44 | (5) |
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49 | (2) |
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3 Hardware accelerator systems for artificial intelligence and machine learning |
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51 | (46) |
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52 | (1) |
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53 | (13) |
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3 Hardware inference accelerators for deep neural networks |
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66 | (12) |
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4 Hardware inference accelerators using digital neurons |
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78 | (10) |
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88 | (1) |
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89 | (1) |
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90 | (4) |
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94 | (3) |
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4 Generic quantum hardware accelerators for conventional systems |
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97 | (38) |
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98 | (1) |
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2 Principles of computation |
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98 | (2) |
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3 Need and foundation for quantum hardware accelerator design |
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100 | (18) |
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4 A generic quantum hardware accelerator (GQHA) |
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118 | (7) |
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5 Industrially available quantum hardware accelerators |
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125 | (5) |
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6 Conclusion and future work |
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130 | (1) |
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130 | (3) |
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133 | (2) |
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5 FPGA based neural network accelerators |
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135 | (32) |
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136 | (1) |
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137 | (5) |
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3 Algorithmic optimization |
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142 | (5) |
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4 Accelerator architecture |
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147 | (7) |
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154 | (3) |
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157 | (1) |
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158 | (2) |
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8 Future research directions |
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160 | (1) |
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160 | (4) |
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164 | (3) |
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6 Deep learning with GPUs |
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167 | (50) |
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1 Deep learning applications using GPU as accelerator |
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168 | (3) |
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2 Overview of graphics processing unit |
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171 | (10) |
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3 Deep learning acceleration in GPU hardware perspective |
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181 | (7) |
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4 GPU software for accelerating deep learning |
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188 | (8) |
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5 Advanced techniques for optimizing deep learning models on GPUs |
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196 | (11) |
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6 Cons and pros of GPU accelerators |
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207 | (1) |
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208 | (1) |
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209 | (4) |
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Further reading/References for advance |
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213 | (1) |
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213 | (4) |
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7 Architecture of neural processing unit for deep neural networks |
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217 | (30) |
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218 | (1) |
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219 | (3) |
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3 Considerations in hardware design |
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222 | (1) |
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223 | (12) |
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235 | (3) |
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238 | (1) |
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239 | (1) |
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239 | (4) |
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243 | (2) |
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245 | (2) |
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8 Energy-efficient deep learning inference on edge devices |
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247 | (56) |
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248 | (1) |
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249 | (9) |
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3 Deep learning frameworks and libraries |
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258 | (1) |
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4 Advantages of deep learning on the edge |
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259 | (1) |
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5 Applications of deep learning at the edge |
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260 | (2) |
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6 Hardware support for deep learning inference at the edge |
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262 | (3) |
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7 Static optimizations for deep learning inference at the edge |
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265 | (17) |
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8 Dynamic (input-dependent) optimizations for deep learning inference at the edge |
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282 | (11) |
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9 Open challenges and future directions |
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293 | (1) |
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293 | (8) |
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301 | (2) |
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9 "Last mile" optimization of edge computing ecosystem with deep learning models and specialized tensor processing architectures |
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303 | (40) |
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304 | (2) |
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306 | (5) |
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311 | (8) |
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319 | (11) |
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330 | (2) |
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332 | (1) |
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333 | (1) |
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333 | (6) |
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339 | (1) |
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339 | (4) |
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10 Hardware accelerator for training with integer backpropagation and probabilistic weight update |
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343 | (24) |
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344 | (3) |
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2 Integer back propagation with probabilistic weight update |
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347 | (7) |
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3 Consideration of hardware implementation of the probabilistic weight update |
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354 | (2) |
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4 Simulation results of the proposed scheme |
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356 | (3) |
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359 | (2) |
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361 | (1) |
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361 | (1) |
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362 | (2) |
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364 | (3) |
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11 Music recommender system using restricted Boltzmann machine with implicit feedback |
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367 | (34) |
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368 | (3) |
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2 Types of recommender systems |
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371 | (15) |
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386 | (1) |
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386 | (4) |
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390 | (5) |
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6 Minibatch size used for training and selection of weights and biases |
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395 | (1) |
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7 Types of activation function that can be used in this model |
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395 | (1) |
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8 Evaluation metrics that can be used to measure for music recommendation |
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396 | (1) |
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397 | (1) |
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398 | (1) |
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399 | (1) |
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399 | (1) |
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399 | (2) |
| About the authors |
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401 | |
Shiho Kim is a professor in the school of integrated technology at Yonsei University, Seoul, Korea. His previous assignment includes, System on chip design engineer, at LG Semicon Ltd. (currently SK Hynix), Korea, Seoul [ 1995-1996], Director of RAVERS (Research center for Advanced Hybrid Electric Vehicle Energy Recovery System, a government-supported IT research center. Associate Director of the ICT consilience program, which is a Korea National program for cultivating talented engineers in the field of information and communication Technology, Korea [ 2011-2012], Director of Seamless Transportation Lab, at Yonsei university, Korea [ since 2011-]. His main research interest includes Development of software and hardware technologies for intelligent vehicles, Blockchain technology for intelligent transportation systems, and reinforcement learning for autonomous vehicles. He is the member of the editorial board and reviewer for various Journals and International conferences. So far he has organized 2 International Conference as Technical Chair/General Chair. He is a member of IEIE (Institute of Electronics and Information Engineers of Korea), KSAE (Korean Society of Automotive Engineers), vice president of KINGC (Korean Institute of Next Generation Computing), and a senior member of IEEE. He is the co-author for over 100 papers and holding more than 50 patents in the area of information and communication technology. Ganesh Chandra Deka is currently Deputy Director (Training) at Directorate General of Training, Ministry of Skill Development and Entrepreneurship, Government of India, New Delhi-110001, India. His research interests include e-Governance, Big Data Analytics, NoSQL Databases and Vocational Education and Training.
He has 2 books on Cloud Computing published by LAP Lambert, Germany. He is the Co-author for 4 text books on Fundamentals of Computer Science (3 books published by Moni Manik Prakashan, Guwahati, Assam, India and 1 IGI Global, USA). As of now he has edited 14 books (6 IGI Global, USA, 5 CRC Press, USA, 2 Elsevier & 1 Springer) on Big data, NoSQL and Cloud Computing and authored 10 Book Chapters.
He has published around 47 research papers in various IEEE conferences. He has organized 08 IEEE International Conferences as Technical Chair in India. He is the Member of the editorial board and reviewer for various Journals and International conferences. Member of IEEE, the Institution of Electronics and Telecommunication Engineers, India and Associate Member, the Institution of Engineers, India
