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Hardware Software Co-Design of a Multimedia SOC Platform 2009 ed. [Kõva köide]

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  • Formaat: Hardback, 152 pages, kõrgus x laius: 235x155 mm, kaal: 930 g, XX, 152 p., 1 Hardback
  • Ilmumisaeg: 12-Feb-2009
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1402096224
  • ISBN-13: 9781402096228
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Hardware Software Co-Design of a Multimedia SOC Platform 2009 ed.Suurem pilt
  • Formaat: Hardback, 152 pages, kõrgus x laius: 235x155 mm, kaal: 930 g, XX, 152 p., 1 Hardback
  • Ilmumisaeg: 12-Feb-2009
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1402096224
  • ISBN-13: 9781402096228
Teised raamatud teemal:
Püsilink: https://www.kriso.ee/db/9781402096228.html
Märksõnad:
Hardware Software Co-Design of a Multimedia SOC Platform is one of the first of its kinds to provide a comprehensive overview of the design and implementation of the hardware and software of an SoC platform for multimedia applications. Topics covered in this book range from system level design methodology, multimedia algorithm implementation, a sub-word parallel, single-instruction-multiple data (SIMD) processor design, and its virtual platform implementation, to the development of an SIMD parallel compiler as well as a real-time operating system (RTOS). Hardware Software Co-Design of a Multimedia SOC Platform is written for practitioner engineers and technical managers who want to gain first hand knowledge about the hardware-software design process of an SoC platform. It offers both tutorial-like details to help readers become familiar with a diverse range of subjects, and in-depth analysis for advanced readers to pursue further.
1 Introduction 1
2 Design Consideration 5
2.1 Platform-Based Design
5
2.1.1 OMAP
8
2.2 System Modeling
10
2.2.1 State-Oriented Models
11
2.2.2 Activity-Oriented Models
12
2.3 Video Coding
15
2.3.1 H.264 Coding Process
17
2.3.2 Motion Estimation
17
2.3.3 Intra Prediction
22
2.3.4 Transform and Quantization
24
2.3.5 De-Blocking Filter
26
2.3.6 Entropy Encoding
27
2.4 Image Processing
27
2.5 Cryptography
31
2.5.1 RSA
32
2.5.2 DES
34
2.5.3 AES
34
2.6 Digital Communication
36
2.7 Multimedia Instruction Set Design
39
3 System Level Design 41
3.1 Abstraction Levels
42
3.1.1 Algorithm Level
42
3.1.2 Architecture Level
42
3.1.3 Behavior Level
44
3.2 Algorithm Level Verification
45
3.2.1 Algebraic Simulation
46
3.2.2 Algebraic Analysis
48
3.2.3 Error Evaluation
48
3.3 Transaction Level Modeling
52
3.4 System Level Development Tools
55
3.4.1 SystemC
56
3.4.2 LISA
58
4 Embedded Processor Design 63
4.1 Specific Instruction-Set
63
4.2 Data Level Parallelism
64
4.2.1 SIMD
64
4.2.2 SWP-SIMD
67
4.3 Instruction Level Parallelism
70
4.3.1 SuperScalar
70
4.3.2 VLIW
71
4.3.3 NISC
74
4.4 Thread Level Parallelism
76
4.4.1 Multi-Threading
76
4.4.2 Multi-Processor
77
4.4.3 Massively Parallel
78
5 Parallel Compiler 81
5.1 Vectorization
81
5.1.1 Dependence Analysis
81
5.1.2 Loop Normalization
83
5.1.3 Loop Transformation
84
5.1.4 Dependence Removal
84
5.1.5 Strongly Connected Components
85
5.1.6 Loop Distribution
86
5.2 Simdization
87
5.2.1 Control Flow Conversion
87
5.2.2 Memory Alignment
88
5.2.3 Permutation Optimization
89
5.2.4 Subword Fusion
90
5.2.5 Matrix Transpose
90
5.2.6 Reduction
90
5.2.7 Loop Unrolling
91
5.3 ILP Scheduling
92
5.3.1 Software Pipelining
92
5.3.2 Basic Block Extension
93
5.3.3 Speculation
93
5.4 Threading
94
5.4.1 Profiling and Analysis
94
5.4.2 Pthread
95
5.4.3 Structuring
97
5.4.4 OpenMP
99
5.5 Compiler Technique
100
5.5.1 Lexical Analysis
100
5.5.2 Syntax Analysis
101
5.5.3 Abstract Syntax
102
5.5.4 Semantic Analysis
103
5.5.5 Symbol-Table Management
104
5.5.6 Intermediate Representation
104
5.5.7 Code Optimization
105
5.5.8 Code Generation
106
5.6 Compiler Infrastructures
106
5.6.1 LCC Compiler Infrastructure
107
5.6.2 GCC Compiler Infrastructure
107
5.6.3 SUIF Compiler Infrastructure
109
5.6.4 IMPACT Compiler Infrastructure
113
6 Implementation of H.264 on PLX 115
6.1 Instruction Set Decision for H.264
115
6.2 Hardware/Software Partitioning
116
6.3 Untimed Virtual Prototype
117
6.4 Timed SystemC Modeling
122
6.5 PLX Chip Design
127
7 Real-Time Operating System for PLX 129
7.1 PRRP Scheduler
131
7.2 Memory Management
133
7.3 Communication and Synchronization Primitives
134
7.4 Multimedia Applications in RTOS for PLX
135
7.5 Application Development Environment
136
7.5.1 Compilers
137
7.5.2 Parser, Locator, Loader, and Startup Code
137
7.5.3 PLX Platform Simulator
139
7.6 Experimental Results
139
8 Conclusion 145
References 147
Prof. Sao-Jie Chen has (co)authored numerous books for Springer