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High Quality Test Pattern Generation and Boolean Satisfiability 2012 [Kõva köide]

  • Formaat: Hardback, 193 pages, kõrgus x laius: 235x155 mm, kaal: 488 g, XVIII, 193 p., 1 Hardback
  • Ilmumisaeg: 31-Jan-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1441999752
  • ISBN-13: 9781441999757
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  • Formaat: Hardback, 193 pages, kõrgus x laius: 235x155 mm, kaal: 488 g, XVIII, 193 p., 1 Hardback
  • Ilmumisaeg: 31-Jan-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • ISBN-10: 1441999752
  • ISBN-13: 9781441999757
This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). It presents a fast and highly fault efficient SAT-based ATPG framework.

This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT).  A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects. The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages: Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT); Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly;Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model;Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.
1 Introduction
1(10)
Part I Preliminaries and Previous Work
2 Circuits and Testing
11(30)
2.1 Post-Production Test
11(3)
2.2 Circuits
14(2)
2.2.1 Scan-Based Testing
15(1)
2.3 Fault Models
16(9)
2.3.1 Stuck-at
17(3)
2.3.2 Delay
20(5)
2.4 Classical ATPG Algorithms
25(11)
2.4.1 ATPG for Stuck-at Faults
25(7)
2.4.2 ATPG for Delay Faults
32(4)
2.5 Industrial Test Environment
36(5)
3 Boolean Satisfiability
41(18)
3.1 Boolean Algebra
41(1)
3.2 SAT Solver
42(2)
3.2.1 DLL-Algorithm
43(1)
3.3 Advanced SAT Techniques
44(8)
3.3.1 Fast Boolean Constraint Propagation
45(1)
3.3.2 Conflict Analysis
46(3)
3.3.3 Conflict-Driven Heuristics
49(2)
3.3.4 Incremental SAT
51(1)
3.3.5 Restarts
52(1)
3.4 Circuit-to-CNF Transformation
52(2)
3.5 Circuit-Oriented SAT and Observability Don't Cares
54(5)
3.5.1 Exploitation of Observability Don't Cares
56(3)
4 ATPG Based on Boolean Satisfiability
59(14)
4.1 SAT-Based ATPG for Boolean Circuits
60(6)
4.1.1 SAT Formulation: Stuck-at Fault Model
60(3)
4.1.2 SAT-Based ATPG Techniques
63(3)
4.2 SAT-Based ATPG for Industrial Circuits
66(3)
4.2.1 Multiple-Valued Logic
66(2)
4.2.2 Hybrid Logic
68(1)
4.2.3 Improving Compactness
68(1)
4.3 Combination with Structural Algorithm
69(4)
Part II New SAT Techniques and their Application in ATPG
5 Dynamic Clause Activation
73(34)
5.1 Overall Framework for Dynamic Clause Activation
74(3)
5.2 Efficient Activation Methodology
77(5)
5.2.1 Consistent SAT Instance
78(1)
5.2.2 Structural Watch List
79(3)
5.3 Literal-Based Activation
82(2)
5.4 Implicit Observability Don't Cares
84(5)
5.4.1 Clause-Based J-Frontier
85(3)
5.4.2 SCOAP-Based Decision Heuristic
88(1)
5.5 Classical SAT Solver Emulation
89(2)
5.6 SAT Formulation for Test Generation Using DCA
91(3)
5.6.1 Dynamic Clause Activation and Multiple-Valued Logic
93(1)
5.7 Experimental Results
94(11)
5.7.1 Results for the Stuck-at Fault Model
95(3)
5.7.2 Results for the Path Delay Fault Model
98(2)
5.7.3 Results for Industrial Circuits
100(5)
5.8 Summary
105(2)
6 Circuit-Based Dynamic Learning
107(20)
6.1 Integration of Dynamic Learning
108(4)
6.1.1 Pervasive Conflict Clause Identification
108(2)
6.1.2 Variable-Based Activation
110(1)
6.1.3 Combination with Dynamic Clause Activation
111(1)
6.2 Post-Classification Phase
112(1)
6.3 Learning Strategies
113(1)
6.4 Improved SAT Solving Engine
114(1)
6.5 Experimental Results
115(8)
6.5.1 Dynamic Learning for Stuck-at Faults
116(2)
6.5.2 Dynamic Learning for Path Delay Faults
118(1)
6.5.3 Dynamic Learning for Industrial Circuits
119(3)
6.5.4 Combination of Structural and SAT-Based Algorithms
122(1)
6.6 Summary
123(4)
Part III High Quality Delay Test Generation
7 High Quality ATPG for Transition Faults
127(28)
7.1 Transition Fault Model: SAT Formulation
128(6)
7.1.1 Iterative Logic Array
128(1)
7.1.2 Injection of Stuck-at Faults
129(2)
7.1.3 Experimental Results
131(3)
7.2 Long Propagation Paths
134(6)
7.2.1 Incremental Instance Generation
135(1)
7.2.2 Output Ordering
136(1)
7.2.3 Experimental Results
137(3)
7.3 Timing-Aware ATPG
140(12)
7.3.1 Motivational Example
140(2)
7.3.2 Pseudo-Boolean Optimization
142(1)
7.3.3 PBO Formulation: Timing-Aware ATPG
143(6)
7.3.4 Using Structural Information
149(1)
7.3.5 Considering Transition-Dependent Delays
150(1)
7.3.6 Experimental Results
151(1)
7.4 Summary
152(3)
8 Path Delay Fault Model
155(26)
8.1 Related Work
156(2)
8.1.1 Robust Tests in Combinational Circuits
157(1)
8.1.2 Incremental SAT and Learning
157(1)
8.1.3 PDF Test Generation Using CSAT
158(1)
8.2 Non-Robust Test Pattern Generation
158(2)
8.3 Robust Test Pattern Generation
160(2)
8.4 SAT Instance Generation Flow
162(1)
8.5 As-Robust-As-Possible Test Generation
163(9)
8.5.1 Test Generation for ARAP Tests
166(2)
8.5.2 Incremental SAT Formulation for Static Value Justification
168(2)
8.5.3 Considering the Presence of Small Delay Defects
170(2)
8.6 Experimental Results
172(7)
8.6.1 Comparison with Competitive Approach
173(1)
8.6.2 SAT Instance Generation Flow
173(2)
8.6.3 MONSOON Using DynamicSAT
175(2)
8.6.4 ARAP Test Generation
177(2)
8.7 Summary
179(2)
9 Summary and Outlook
181(2)
References 183(8)
Index 191