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Chapter 1 Challenges of DSP Systems Design |
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1 | (12) |
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1.1 High-Speed Dsp Systems Overview |
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2 | (3) |
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1.2 Challenges Of Dsp Audio System |
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5 | (1) |
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1.3 Challenges Of Dsp Video System |
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6 | (2) |
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1.4 Challenges Of Dsp Communication System |
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8 | (3) |
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11 | (2) |
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Chapter 2 Transmission Line (TL) Effects |
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13 | (18) |
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2.1 Transmission Line Theory |
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14 | (5) |
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2.2 Parallel Termination Simulations |
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19 | (2) |
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2.3 Practical Considerations Of TL |
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21 | (1) |
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2.4 Simulations And Experimental Results Of TL |
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22 | (5) |
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2.4.1 TL Without Load Or Source Termination |
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22 | (2) |
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2.4.2 TL With Series Source Termination |
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24 | (3) |
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2.5 Ground Grid Effects On TL |
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27 | (1) |
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2.6 Minimizing TL Effects |
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28 | (2) |
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30 | (1) |
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Chapter 3 Effects of Crosstalk |
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31 | (14) |
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31 | (5) |
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3.2 Crosstalk Caused By Radiation |
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36 | (5) |
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41 | (2) |
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43 | (2) |
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Chapter 4 Power Supply Design Considerations |
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45 | (22) |
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4.1 Power Supply Architectures |
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45 | (10) |
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4.2 DSP Power Supply Architectural Considerations |
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55 | (9) |
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4.2.1 Power Sequencing Considerations |
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61 | (3) |
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64 | (1) |
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65 | (2) |
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Chapter 5 Power Supply Decoupling |
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67 | (38) |
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5.1 Power Supply Decoupling Techniques |
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67 | (27) |
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5.1.1 Capacitor Characteristics |
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69 | (3) |
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5.1.2 Inductor Characteristics |
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72 | (2) |
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5.1.3 Ferrite Bead Characteristics |
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74 | (1) |
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5.1.4 General Rules-Of-Thumb Decoupling Method |
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75 | (2) |
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5.1.5 Analytical Method of Decoupling |
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77 | (14) |
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5.1.6 Placing Decoupling Capacitors |
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91 | (3) |
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5.2 High Frequency Noise Isolation |
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94 | (8) |
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95 | (3) |
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98 | (4) |
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102 | (2) |
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104 | (1) |
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Chapter 6 Phase-Locked Loop (PLL) |
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105 | (16) |
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105 | (6) |
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107 | (4) |
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111 | (3) |
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6.3 PLL Isolation Techniques |
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114 | (5) |
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114 | (4) |
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6.3.2 Linear Voltage Regulator |
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118 | (1) |
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119 | (1) |
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120 | (1) |
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Chapter 7 Data Converter Overview |
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121 | (20) |
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121 | (1) |
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7.2 Analog-To-Digital Converter (ADC) |
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122 | (8) |
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124 | (2) |
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126 | (4) |
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7.3 Digital-To-Analog Converter (DAC) |
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130 | (2) |
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7.4 Practical Data Converter Design Considerations |
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132 | (6) |
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7.4.1 Resolution and Signal-to-Noise |
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133 | (1) |
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134 | (1) |
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7.4.3 Input and Output Voltage Range |
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134 | (1) |
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7.4.4 Differential Non-Linearity (DNL) |
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135 | (2) |
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7.4.5 Integral Non-Linearity (INL) |
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137 | (1) |
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138 | (2) |
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140 | (1) |
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Chapter 8 Analog Filter Design |
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141 | (36) |
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8.1 Anti-Aliasing Filters |
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141 | (34) |
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8.1.1 Passive and Active Filters Characteristics |
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142 | (1) |
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8.1.2 Passive Filter Design |
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143 | (3) |
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8.1.3 Active Filter Design |
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146 | (1) |
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8.1.4 Operation Amplifier (op amp) Fundamentals |
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147 | (8) |
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155 | (9) |
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8.1.6 First Order Active Filter Design |
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164 | (5) |
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8.1.7 Second Order Active Filter Design |
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169 | (6) |
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175 | (1) |
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176 | (1) |
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Chapter 9 Memory Sub-System Design Considerations |
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177 | (10) |
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177 | (4) |
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179 | (2) |
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181 | (1) |
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9.2 DDR Memory Signal Integrity |
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181 | (2) |
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9.3 DDR Memory System Design Example |
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183 | (3) |
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186 | (1) |
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Chapter 10 Printed Circuit Board (PCB) Layout |
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187 | (8) |
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10.1 Printed Circuit Board (PCB) Stackup |
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187 | (3) |
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10.2 Microstrip And Stripline |
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190 | (2) |
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192 | (1) |
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193 | (1) |
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194 | (1) |
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Chapter 11 Electromagnetic Interference (EMI) |
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195 | (16) |
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11.1 FCC Part 15B Overview |
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195 | (2) |
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197 | (2) |
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199 | (2) |
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201 | (1) |
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202 | (2) |
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204 | (2) |
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11.7 Power And Ground Planes |
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206 | (2) |
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11.8 Summary: EMI Reduction Guidelines |
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208 | (2) |
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210 | (1) |
Glossary |
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211 | (2) |
Index |
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213 | |