Overview of SEMI and the IEEE Process Specific Yield Learning Invited: Evaluation of the Yield Impact of Epitaxal Defects on Advanced Semiconductor Technologies 1(7) R. Williams R. Jacques W. Chen M. Akbulut Case Study For Root Cause Analysis of Yield Problems 8(6) D. Malinaric R. Hoffmeister C. Sun Yield Enhancement Through Understanding The Particle Adhesion and Removal Mechanisms in CMP and Post-CMP Cleaning Processes 14(4) J. Taylor A. Busnaina The Use of Historical Defect Imagery for Yield Learning 18(8) K. Tobin T. Karnowski F. Lakhani The 100 Yield Explanation Approach in Lucent Technologies Madrid 26(7) M. Recio M. Merino V. Martin J. Ayucar J. Moreno A. Godino C. Mata C. Morilla A. Lorenzo R. Fernandez J. Inarrea M. Alvarez A. Sacedon C. Mateos K. Therryl G. Gonzalez S. Cruceta Advanced Process Control Based on Lithographic Defect Inspection and Reduction 33(13) A. Skumanich J. Boyle J. Leavy Factory Dynamics Invited: Yield and Equipment Utilization Improvements Achieved Through Fab Conversion to Carbon Fiber/CF/Peek Wafer Carriers and Carbon Fiber/Polypropylene Storage Boxes 41(5) E. Merrill J. Bostwick C. Gilhoi K. Mikkelsen Solving Tough Semiconductor Manufacturing Problems Using Data Mining 46(10) R. Gardner J. Bieker S. Elwell R. Thalman E. Rivera Measuring Efficiency of Semiconductor Manufacturing Operations Using Data Envelopment Analysis (DEA) 56(7) T. Carbone Maximizing Productivity Improvements Using Short Cycle Time Manufacturing (SCM) Concepts in a Semiconductor Manufacturing Line 63(5) D. Martin Effective Methodology For Movement of Rapid Turn Around Time (RTAT) Hardware in a Multi-flow Fabricator 68(7) J. LaFreniere L. Labanowski The Positive Cycle Time Impact of Closely Monitoring Your Factorys Critical Tools 75(8) J. Berry N. Pierce L. Serrano S. Stankus R. Darrington W. Scott B. Sinclair Yield Analysis and Modeling Invited: Technology Assessment of Commercially Available Critical Area Extraction Tools 76(7) C. Long D. Maynard M.A. Bjornsen Critical Area Based Yield Prediction Using In-line Defect Classification Information 83(6) J. Segal A. Sagatelian B. Hodgkins B. Chu T. Singh H. Berman A Technology Development Sram Approach With DFM Considerations 89(3) M. Craig D.Deshazo S. Prior B. Tranchina M. Erhart S.S. Mahant-Shetti R. Taylor Y. Xing E. Quek K.L. Chok N. Kamat M. Redford The Identification and Analysis of Systematic Yield Loss 92(4) R. Langford G. Hsu C. Sun A Defect-to-Yield Correlation Study for Marginally Printing Reticle Defects in the Manufacture of a 16MB Flash 96(7) J. Erhardt K. Phan E. Backe Q. Tran B. Fletcher B. Hopper I. Peterson A. Zuo Combination of TCAD and Physical Mosfet Model for LSI Development Time Reduction 103(13) K. Ishimaru K. Kasai Y. Fukaura Y. Okayama T. Imamura S. Irie T. Hirano K. Watanabe M. Ueno K. Hashimoto F. Matsuoka Defect Source Methodology Invited: Defect Localization Using Physical Design and Electrical Test Information 108(8) Z. Stanojevic D. M. H. Walker H. Balachandran S. Jandhyala F. Lakhani Optimizing Automatic Defect Classification Feature and Classifier Performance For Post-Fab Yield Analysis 116(8) M. A. Hunt T. P. Karnowski C. Kiest L. Villalobos In-line Wafer Inspection Data Warehouse For Automated Defect Limited Yield Analysis 124(6) H. Iwata M. Ono J. Konishi S. Isogai T. Furutani Multiple Applications of an Automatic Defect Review of SEM in Semiconductor Manufacturing Yield Enhancement 130(1) B. Hance In-Line SEM Based ADC For Advanced Process Control 131(7) A. Skumanich D. Farrington W. Tomlinson B. Halliday Poster Session The Application and Use of ATPG Data In Problem Solving Efforts To Improve Yields on Advanced Microprocessors 138(1) M. McIntyre E. Ehrichs Bitmapped Yield Enhancement Solutions: A Case Study of Escalating Yield 139(2) L. Jacobson D. Crain C. Joyce Comparative Study of Two KLA-Tencor Advanced Patterned Wafer Inspection Systems 141(1) S. Rowley S. Thorne A. Bousetta C. Perry C. Dutton A Comparison of Extra Material Critical Area Extraction Methods 142(10) G. Allan A Comparison of Inspection Strategy Models for Optimized Tool Utilization 152(1) A. Skumanich Contact Size Dependence of Highly Selective Self-Aligned Contact Etching with Polymer Formation and Its Mechanism 153(4) Y.H. Liu Y.L. Tu W.Y. Lain B.W. Chain M. Chi Critical Factors in Successful Transfer of Semiconductor Products Across Factories 157(5) M. Pullon G. Kong Effects of Dilute HCI Wafer Cleaning Solutions on Borophosphosilicate Glass Films 162(6) R. Webb R. Glahn R.S. Ridley, Sr. Fab Automation - Wheres the Payback 168(7) D. Scott The Impact of Tolerance on Kill Ratio Estimation for Memory 175(6) O. Patterson M. Hansen Implementation of Best Known Methods 181(6) J. Foster T. Nugent P. Marxoux Managing Arsenic in GaAs Fab Wastewater 187(6) J. Peterson Preparing the Workforce for Semiconductor/VLSI Industry for the 21st Century at UMASS Lowell 193(1) K. Prasad SmartBit™: Bitmap to Defect Correlation Software For Yield Improvement 194(5) M. Merino S. Cruceta A. Garcia M. Recio Tighter Process Control and Reduced Cycle Times Using Off-line Recipe Setup 199(4) S. Stevens R. Harper P. Knutrud A. Carlson Trace Gas Detection with CW Cavity Ring-Down Laser Absorption Spectroscopy 203(4) W.B. Yan J. Dudek K. Lehmann P. Rabinowitz Wafer Probe Process Verification Tools 207(12) R. Enrique C. Carlos S.V. Javier M. Julian Educating and Training the Workforce Invited: 3 Massachusetts Semiconductor Manufacturing Companies Improve Their Workforce Productivity Through Collaboration with Community Colleges 213(6) A. Yu S. Gharib L. Solomon S. Dutru J. Burke D. Planchard M. OConnor The Implementation of a Performance Management System in an 8 Inch Fabrication Facility Within A Unionized Workforce 219(8) A. Acri A. Markowski R. Rerick The Role of Retired Engineers in Pre-College Science and Mathematics Education 227(4) C. Zahopoulos D. Weeden Re-Seed Effects of Operator Grouping on the VLSI Final Test Facility Layout Scale 231(14) K. Nakamae W. Koga H. Fujioka Cost and Profitability Invited: Effect of Fab Scale, Process Diversity and Setup on Semiconductor Wafer Processing Cost 237(8) Y. Iwata S. Wood Value-Based Dispatching for Semiconductor Wafer Fabrication 245(5) N. Pierce T. Yurtsever Maximizing Profitability Through Easy Information Transfer 250(6) C. Weber E. von Hippel Optimizing the Cost of Design Rule Modifications For Subsequent Generations of Semiconductor Technology 256(8) A. Balasinski Advanced Process: Photo/Etch Invited: An Integrated Hardmask/Poly RIE Process for Sub0.25μum Gate Etch 263(1) S. Shah J. Andrews MiCrus M. Goss R. Kurjansky Stepper Exposure Field Uniformity Mapping Using Electrical Critical Dimension Measurements 264(10) B. McCarson T. Salisbury GC Hard Mask Open Tool CD Monitoring and Matching 274(4) C. Yu D. Bennett J. Brown 2-in-1 Total Process Integration in Merie Etch Chamber For Cu Dual Damascene Applications 278(3) R. Wu L. Zhang J. Yang J. Tsui A. Jiang J. Sun J. Yuan P. Hsieh R. Hung Y. Ye G. Hsueh J. Shieh J. Liu C. Tsai A Dry Process For Polymer Sidewall Residue Removal After Via-Hole Etching 281(6) X. Han M. Boumerzoug R. Bersin L. Mikus A. Horn D. Dopp Optical CD Applications for <200nm Lithography Control and Productivity Improvement <200nm Lithography Control and Productivity Improvement 287(15) E. Morita F. Leung C. Fruga B. Gwynn H. Pournasr R. Pierce Defect Reduction for Yield Enhancement Invited: Investigation and Elimination of Sphere Defects 296(6) F. Lee M. Newtran T. Hulseweh Evaluation of the `HiVol Above-Wafer In-situ Monitoring Sensor 302(10) R. Williams E. Wickesberg R. Jacques M. Bonin D. Holve Defect Reduction Methodology For Advanced Copper Dual Damascene Oxide Etch 312(11) P. Biolisi S. Ellinger D. Morvay Defect Control Methods for Simox SOI Wafer Manufacture and Processing 323(5) M. Alles J. Dunne S. MacNish M. Burns Surface Cleaning Mechanisms and Future Cleaning Requirements 328(6) A.A. Busnaina H. Lin N. Moumen Elimination of Contamination in the Epitaxial Process For High-Volume Power Semiconductor Device Manufacturing 334(13) R. Glahn R. S. Ridley, Sr. Advanced Process: FEOL Deposition and Cleaning Invited: Tungsten Silicide Gate Stack Optimization for 170-nm Dram Technology 340(7) V. Rao J. Morgan J. Barden Y. Karzhavin P. Van Holt R. Petter H. Ollendorf K. Christensen D. Ricks W. Hoesler Advanced Multi-Objective Control for Epitaxial Silicon Deposition 347(10) A. Gower D. Boning P. Rosenthal A. Waldhauer Developing a Manufacturable Process for the Deposition of Thick Polysilicon Films for Micro Machined Devices 357(10) K. Nunan G. Ready P. Garone G. Sturdy J. Sledziewski The Influence of the Pre-Anneal Ambient on the Gate Oxide Integrity Effect of Copper Contamination 367(5) B. Vermiere H.G. Parks Effect of HC1 and Chemical Clean on Thin Oxide Growth 372(15) R. Naujokaitis R. Cosway Process Control Invited: A Tolerance Analysis for Manufacturing to Direct Process Capability Improvement Efforts 377(10) K. Hirshman Optimization of MOS Capacitor Based Short Flow for Monitoring Ion Implantation-induced Charging 387(5) T. Brozek C. Norton A Novel Method for Statistical Process Control of Gate Oxide and Front-end Cleans Monitoring in a Manufacturing Environment 392(5) R. Cosway L. Pirastehfar R. Root T. Roche R. Naujokaitis A Sensor Fusion Based Methodology for Real Time Furnace Diagnostics 397(10) J. Wang C. Spanos Quantifying the Capability of a New In-situ Interferometer 407(12) W. Roberts C. Gould K. Rebitz A. Smith J. Guerro Advanced Process: Chemical Mechanical Polishing (CMP) Invited: Interconnect Strategies for Deep Submicron CMOS Manufacture 413(6) K. Rose C. Mark Evaluation of an Advanced Wafer Carrier Design for ILD Planarization 419(3) M. Jaso T. Glynn J. Giunta D. Diefenderfer Development of Slurry Concentration Adjustable Tungsten Chemical Mechanical Planarization (CMP) Process 422(3) X. Wang J. Tan P. Tan C. Lin H. Zhao Nanotopography Effects on Chemical Mechanical Polishing for Shallow Trench Isolation 425(8) B. Lee T. Gan D. Boning P. Hester N. Poduje W. Baylies Post-Chemical-Mechanical Planarzation Cleaning Application in Metallization 433(4) C. Huynh J. Chapple-Sokol K. Pope Copper CMP Planarity Control Using ITM 437(14) A. Ravid A. Sharon A. Weingarten V. Machavariani D. Scheiner Equipment Productivity and Effectiveness Invited: STM Crolles TPM Development and Success Story 444(7) C. Ribes Pilot Studies of the Manufacturing Worthiness of Mixed Chemistry Processing in a Merie Plasma Tool 451(4) J. Yang L. Zhang J. Tsui A. Jiang J. Sun K. Vaidya R. Wu Capacity Planning Model: The Important Inputs, Formulas, and Benefits 455(4) T. Occhino Productivity Improvement Focus at White Oak Semiconductor 459(7) Y. Karzhavin Determining the Capacity Components of Multi-Chamber Systems 466(3) D. Martin M. McClintock R. Woods Using Overall Equipment Effectiveness (OEE) and the Equipment Improvement Process (EI) to Improve Fab Throughput 469(3) R. Freck Biographies of Speakers 472
